@@ -74,9 +74,6 @@ (define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]"
(define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]"
"FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.")
-(define_register_constraint "wj" "rs6000_constraints[RS6000_CONSTRAINT_wj]"
- "FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.")
-
(define_register_constraint "wk" "rs6000_constraints[RS6000_CONSTRAINT_wk]"
"FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.")
@@ -2513,7 +2513,6 @@ rs6000_debug_reg_global (void)
"wf reg_class = %s\n"
"wg reg_class = %s\n"
"wi reg_class = %s\n"
- "wj reg_class = %s\n"
"wk reg_class = %s\n"
"wl reg_class = %s\n"
"wm reg_class = %s\n"
@@ -2537,7 +2536,6 @@ rs6000_debug_reg_global (void)
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]],
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wj]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wk]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]],
@@ -3162,7 +3160,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
wf - Preferred register class for V4SFmode.
wg - Float register for power6x move insns.
wi - FP or VSX register to hold 64-bit integers for VSX insns.
- wj - FP or VSX register to hold 64-bit integers for direct moves.
wk - FP or VSX register to hold 64-bit doubles for direct moves.
wl - Float register if we can do 32-bit signed int loads.
wm - VSX register for ISA 2.07 direct move operations.
@@ -3205,8 +3202,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
if (TARGET_DIRECT_MOVE)
{
- rs6000_constraints[RS6000_CONSTRAINT_wj] /* DImode */
- = rs6000_constraints[RS6000_CONSTRAINT_wi];
rs6000_constraints[RS6000_CONSTRAINT_wk] /* DFmode */
= rs6000_constraints[RS6000_CONSTRAINT_ws];
rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS;
@@ -1254,7 +1254,6 @@ enum r6000_reg_class_enum {
RS6000_CONSTRAINT_wf, /* VSX register for V4SF */
RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */
RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */
- RS6000_CONSTRAINT_wj, /* FPR/VSX register for DImode direct moves. */
RS6000_CONSTRAINT_wk, /* FPR/VSX register for DFmode direct moves. */
RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */
RS6000_CONSTRAINT_wm, /* VSX register for direct move */
@@ -834,7 +834,7 @@ (define_insn_and_split "*zero_extendhi<mode>2_dot2"
(define_insn "zero_extendsi<mode>2"
- [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,wz,wa,wj,r,wa")
+ [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,wz,wa,wi,r,wa")
(zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,Z,Z,r,wa,wa")))]
""
"@
@@ -846,7 +846,7 @@ (define_insn "zero_extendsi<mode>2"
mfvsrwz %0,%x1
xxextractuw %x0,%x1,4"
[(set_attr "type" "load,shift,fpload,fpload,mffgpr,mftgpr,vecexts")
- (set_attr "isa" "*,*,*,p8v,*,p8v,p9v")])
+ (set_attr "isa" "*,*,*,p8v,p8v,p8v,p9v")])
(define_insn_and_split "*zero_extendsi<mode>2_dot"
[(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
@@ -1019,7 +1019,7 @@ (define_insn_and_split "*extendhi<mode>2_dot2"
(define_insn "extendsi<mode>2"
[(set (match_operand:EXTSI 0 "gpc_reg_operand"
- "=r, r, wl, wa, wj, v, v, wr")
+ "=r, r, wl, wa, wi, v, v, wr")
(sign_extend:EXTSI (match_operand:SI 1 "lwa_operand"
"YZ, r, Z, Z, r, v, v, ?wa")))]
""
@@ -1035,7 +1035,7 @@ (define_insn "extendsi<mode>2"
[(set_attr "type" "load,exts,fpload,fpload,mffgpr,vecexts,vecperm,mftgpr")
(set_attr "sign_extend" "yes")
(set_attr "length" "4,4,4,4,4,4,8,8")
- (set_attr "isa" "*,*,*,p8v,*,p9v,p8v,p8v")])
+ (set_attr "isa" "*,*,*,p8v,p8v,p9v,p8v,p8v")])
(define_split
[(set (match_operand:EXTSI 0 "int_reg_operand")
@@ -5233,7 +5233,7 @@ (define_insn "*xxsel<mode>"
; We don't define lfiwax/lfiwzx with the normal definition, because we
; don't want to support putting SImode in FPR registers.
(define_insn "lfiwax"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,wj,v")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi,wi,v")
(unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,v")]
UNSPEC_LFIWAX))]
"TARGET_HARD_FLOAT && TARGET_LFIWAX"
@@ -5243,7 +5243,7 @@ (define_insn "lfiwax"
mtvsrwa %x0,%1
vextsw2d %0,%1"
[(set_attr "type" "fpload,fpload,mffgpr,vecexts")
- (set_attr "isa" "*,*,*,p9v")])
+ (set_attr "isa" "*,p8v,p8v,p9v")])
; This split must be run before register allocation because it allocates the
; memory slot that is needed to move values to/from the FPR. We don't allocate
@@ -5315,7 +5315,7 @@ (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
(set_attr "type" "fpload")])
(define_insn "lfiwzx"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,wj,wa")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi,wi,wa")
(unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,wa")]
UNSPEC_LFIWZX))]
"TARGET_HARD_FLOAT && TARGET_LFIWZX"
@@ -5325,7 +5325,7 @@ (define_insn "lfiwzx"
mtvsrwz %x0,%1
xxextractuw %x0,%x1,4"
[(set_attr "type" "fpload,fpload,mftgpr,vecexts")
- (set_attr "isa" "*,*,*,p9v")])
+ (set_attr "isa" "*,p8v,p8v,p9v")])
(define_insn_and_split "floatunssi<mode>2_lfiwzx"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
@@ -8831,13 +8831,13 @@ (define_insn "*movdi_internal64"
m, ^d, ^d, wY, Z, $v,
$wv, ^wi, wa, wa, wv, wi,
wi, wv, wv, r, *h, *h,
- ?r, ?wg, ?r, ?wj")
+ ?r, ?wg, ?r, ?wi")
(match_operand:DI 1 "input_operand"
"r, YZ, r, I, L, nF,
^d, m, ^d, ^v, $wv, wY,
Z, ^wi, Oj, wM, OjwM, Oj,
wM, wS, wB, *h, r, 0,
- wg, r, wj, r"))]
+ wg, r, wi, r"))]
"TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], DImode)
|| gpc_reg_operand (operands[1], DImode))"
@@ -8888,7 +8888,7 @@ (define_insn "*movdi_internal64"
*, *, *, p9v, *, p9v,
*, *, p9v, p9v, *, *,
*, *, *, *, *, *,
- *, *, *, *")])
+ *, *, p8v, p8v")])
; Some DImode loads are best done as a load of -1 followed by a mask
; instruction.
@@ -275,11 +275,6 @@ (define_mode_attr VS_double [(V4SI "V8SI")
(V2DF "V4DF")
(V1TI "V2TI")])
-;; Map register class for 64-bit element in 128-bit vector for direct moves
-;; to/from gprs
-(define_mode_attr VS_64dm [(V2DF "wk")
- (V2DI "wj")])
-
;; Map register class for 64-bit element in 128-bit vector for normal register
;; to register moves
(define_mode_attr VS_64reg [(V2DF "ws")
@@ -4158,12 +4153,13 @@ (define_insn "vsx_splat_v4si_di"
[(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,we")
(vec_duplicate:V4SI
(truncate:SI
- (match_operand:DI 1 "gpc_reg_operand" "wj,r"))))]
+ (match_operand:DI 1 "gpc_reg_operand" "wi,r"))))]
"VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
"@
xxspltw %x0,%x1,1
mtvsrws %x0,%1"
- [(set_attr "type" "vecperm")])
+ [(set_attr "type" "vecperm")
+ (set_attr "isa" "p8v,*")])
;; V4SF splat (ISA 3.0)
(define_insn_and_split "vsx_splat_v4sf"
@@ -3197,7 +3197,7 @@ Altivec vector register
Any VSX register if the @option{-mvsx} option was used or NO_REGS.
When using any of the register constraints (@code{wa}, @code{wd},
-@code{wf}, @code{wg}, @code{wi}, @code{wj}, @code{wk},
+@code{wf}, @code{wg}, @code{wi}, @code{wk},
@code{wl}, @code{wm}, @code{wp}, @code{wq}, @code{ws},
@code{wt}, @code{wv}, or @code{ww})
that take VSX registers, you must use @code{%x<n>} in the template so
@@ -3262,9 +3262,6 @@ If @option{-mmfpgpr} was used, a floating point register or NO_REGS.
@item wi
FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.
-@item wj
-FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.
-
@item wk
FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.