From patchwork Fri Aug 21 12:53:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Sayle X-Patchwork-Id: 1349234 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=nextmovesoftware.com header.i=@nextmovesoftware.com header.a=rsa-sha256 header.s=default header.b=PZn70+Yp; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BY1fD0Xvyz9sPf for ; Fri, 21 Aug 2020 22:53:23 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B82A23857C56; Fri, 21 Aug 2020 12:53:19 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 81F273857C43 for ; Fri, 21 Aug 2020 12:53:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 81F273857C43 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=roger@nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=xYkjgE/fGeQg33ablouHmEwpw/WkbKZG9spQQHsX/wE=; b=PZn70+YpE3Z16K36aQGOcMqL/B XSTmNjp/J75Ve/UWVisp+D6qQURb96zg4qqzczjV1SBrvy3ttvJXbNJvlQShdKAit2Y48i+AQuGJe MMD1DY8+7F9XzVn4ZVJtx6ZLUMq9Z92Som27/UvDk0qONtmwJllEOpMwpuMTPB4Pau1AbOkHtqmUr FjAauhzs/zhUX/z9Ux8NT+kDYIh15BVtsFKEDeoaPk/b2FkiHhnSt0RHupE4F5kDupdICEmky8jJz 1gc6j5y7o3IwyfIK3lKmMPR/z81vnuHY3Wt15hEVyirR6r1ihbrjpe8g0OxO2yA/AC2hqKNxw+8s5 LUQTkG1w==; Received: from [185.62.158.67] (port=59413 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1k96Xk-0004Ca-IY; Fri, 21 Aug 2020 08:53:16 -0400 From: "Roger Sayle" To: "'GCC Patches'" Subject: [PATCH] hppa: Improve expansion of ashldi3 when !TARGET_64BIT Date: Fri, 21 Aug 2020 13:53:15 +0100 Message-ID: <044501d677ba$099a5520$1cceff60$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdZ3uVzFVLkvN8DrQ9mTTUzBQh0SbQ== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: 'John David Anglin' Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" This patch improves the code generated on PA-RISC for DImode (double word) left shifts by small constants (1-31). This target has a very cool shd instruction that can be recognized by combine for simple shifts, but relying on combine is fragile for more complicated functions. This patch tweaks pa.md's ashldi3 expander, to form the optimal two instruction shd/zdep sequence at RTL expansion time. As an example of the benefits of this approach, the simple function unsigned long long u9(unsigned long long x) { return x*9; } currently generates 9 instructions u9: copy %r25,%r28 copy %r26,%r29 extru %r26,2,3,%r21 zdep %r25,28,29,%r19 zdep %r26,28,29,%r20 or %r21,%r19,%r19 add %r29,%r20,%r29 addc %r28,%r19,%r28 bv,n %r0(%r2) and with this patch now requires only 7: u9: copy %r25,%r28 copy %r26,%r29 shd %r26,%r25,29,%r19 zdep %r26,28,29,%r20 add %r29,%r20,%r29 addc %r28,%r19,%r28 bv,n %r0(%r2) This improvement is a first step towards getting synth_mult to behave sanely on hppa (PR middle-end/87256). Unfortunately, it's been a long while since I've had access to a hppa system, so apart from building a cross-compiler and looking at the assembler it generates, this patch is completely untested. I was wondering whether Dave or Jeff (or someone else with access to real hardware) might "spin" this patch for me? 2020-08-21 Roger Sayle * config/pa/pa.md (ashldi3): Additionally, on !TARGET_64BIT generate a two instruction shd/zdep sequence when shifting registers by suitable constants. (shd_internal): New define_expand to provide gen_shd_internal. Thanks in advance, Roger --- Roger Sayle NextMove Software Cambridge, UK diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index 6350c68..e7b7635 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -6416,9 +6416,32 @@ [(set (match_operand:DI 0 "register_operand" "") (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "") (match_operand:DI 2 "arith32_operand" "")))] - "TARGET_64BIT" + "" " { + if (!TARGET_64BIT) + { + if (REG_P (operands[0]) && GET_CODE (operands[2]) == CONST_INT) + { + unsigned HOST_WIDE_INT shift = UINTVAL (operands[2]); + if (shift >= 1 && shift <= 31) + { + rtx dst = operands[0]; + rtx src = force_reg (DImode, operands[1]); + emit_insn (gen_shd_internal (gen_highpart (SImode, dst), + gen_highpart (SImode, src), + GEN_INT (32-shift), + gen_lowpart (SImode, src), + GEN_INT (shift))); + emit_insn (gen_ashlsi3 (gen_lowpart (SImode, dst), + gen_lowpart (SImode, src), + GEN_INT (shift))); + DONE; + } + } + /* Fallback to using optabs.c's expand_doubleword_shift. */ + FAIL; + } if (GET_CODE (operands[2]) != CONST_INT) { rtx temp = gen_reg_rtx (DImode); @@ -6705,6 +6728,15 @@ [(set_attr "type" "shift") (set_attr "length" "4")]) +(define_expand "shd_internal" + [(set (match_operand:SI 0 "register_operand") + (ior:SI + (lshiftrt:SI (match_operand:SI 1 "register_operand") + (match_operand:SI 2 "const_int_operand")) + (ashift:SI (match_operand:SI 3 "register_operand") + (match_operand:SI 4 "const_int_operand"))))] + "") + (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")