diff mbox series

[GCC-8,Aarch64] : Backport Force TImode values into even registers

Message ID 02f756ea-bdad-bcce-5cc3-a7db0f250289@arm.com
State New
Headers show
Series [GCC-8,Aarch64] : Backport Force TImode values into even registers | expand

Commit Message

Andre Vieira (lists) April 29, 2020, 12:36 p.m. UTC 
Hi,

This is a backport from trunk/gcc-9 that I think we need now that we 
have backported the casp LSE instructions.

Bootstrapped and regression tested on aarch64.

Is this OK for gcc-8?

Cheers,
Andre

The LSE CASP instruction requires values to be placed in even
register pairs.  A solution involving two additional register
classes was rejected in favor of the much simpler solution of
simply requiring all TImode values to be aligned.

gcc/ChangeLog:
2020-04-29  Andre Vieira  <andre.simoesdiasvieira@arm.com>

     Backport from mainline.
     2018-10-31  Richard Henderson <richard.henderson@linaro.org>

     * config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Force
     16-byte modes held in GP registers to use an even regno.

Comments

Kyrylo Tkachov April 29, 2020, 12:37 p.m. UTC | #1 
> -----Original Message-----
> From: Andre Vieira (lists) <andre.simoesdiasvieira@arm.com>
> Sent: 29 April 2020 13:37
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>
> Subject: [PATCH][GCC-8][Aarch64]: Backport Force TImode values into even
> registers
> 
> Hi,
> 
> This is a backport from trunk/gcc-9 that I think we need now that we
> have backported the casp LSE instructions.
> 
> Bootstrapped and regression tested on aarch64.
> 
> Is this OK for gcc-8?

Ok.
Thanks,
Kyrill

> 
> Cheers,
> Andre
> 
> The LSE CASP instruction requires values to be placed in even
> register pairs.  A solution involving two additional register
> classes was rejected in favor of the much simpler solution of
> simply requiring all TImode values to be aligned.
> 
> gcc/ChangeLog:
> 2020-04-29  Andre Vieira  <andre.simoesdiasvieira@arm.com>
> 
>      Backport from mainline.
>      2018-10-31  Richard Henderson <richard.henderson@linaro.org>
> 
>      * config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Force
>      16-byte modes held in GP registers to use an even regno.
diff mbox series

Patch

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 5eec1aae54abe04b8320deaf8202621c8e193c01..525deba56ea363a621cccec1a923da241908dd06 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -1369,10 +1369,14 @@  aarch64_hard_regno_mode_ok (unsigned regno, machine_mode mode)
   if (regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM)
     return mode == Pmode;
 
-  if (GP_REGNUM_P (regno) && known_le (GET_MODE_SIZE (mode), 16))
-    return true;
-
-  if (FP_REGNUM_P (regno))
+  if (GP_REGNUM_P (regno))
+    {
+      if (known_le (GET_MODE_SIZE (mode), 8))
+	return true;
+      else if (known_le (GET_MODE_SIZE (mode), 16))
+	return (regno & 1) == 0;
+    }
+  else if (FP_REGNUM_P (regno))
     {
       if (vec_flags & VEC_STRUCT)
 	return end_hard_regno (mode, regno) - 1 <= V31_REGNUM;