From patchwork Sat Sep 20 18:23:44 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 391545 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 617E814008B for ; Sun, 21 Sep 2014 04:47:54 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; q=dns; s=default; b=Q/sAnH/iBZwljPP72FS bTEiR/b41QOc3TwEg4myorElCyZnFm78lEAZGUAI5hEBZF4DFs/wy5ySVLOhQoMV F62yWSq4/RcAwBzoazX9eM3FWVDnhin25uMvUxKuK+43EeiIHRxWxQld2Wr/9m4l NJsQJGpTgVV+KvxWn9Eyh0cw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; s=default; bh=nvyD3LxR3SNuWJJ3USODok2XK rM=; b=YnP686i+j/tR2rQDTtBcWknOOqwxnQmFAbkCAXvMIy4nbYZIMzuwGO7JN TYfnM3nwFNoaomIuvW5xael4L4ArkFlwEWyUqCqx8sWxoTYdNvJWMzDyFmpqRFop Zi9cqc5u/Z1cmCL//37BlaAkTMVT2T64M2V9rsO1BJxrWxPHg4= Received: (qmail 23375 invoked by alias); 20 Sep 2014 18:47:16 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 23271 invoked by uid 89); 20 Sep 2014 18:47:15 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: gcc1-power7.osuosl.org Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Sat, 20 Sep 2014 18:47:13 +0000 Received: from gcc1-power7.osuosl.org (localhost [127.0.0.1]) by gcc1-power7.osuosl.org (8.14.6/8.14.6) with ESMTP id s8KIO9pD014882; Sat, 20 Sep 2014 11:24:09 -0700 Received: (from segher@localhost) by gcc1-power7.osuosl.org (8.14.6/8.14.6/Submit) id s8KIO9JQ014859; Sat, 20 Sep 2014 11:24:09 -0700 From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool Subject: [PATCH 5/9] rs6000: Clean up bool3 Date: Sat, 20 Sep 2014 11:23:44 -0700 Message-Id: <0109547357c4f9b719ee523ff49a4c7b726c4791.1411216924.git.segher@kernel.crashing.org> In-Reply-To: <8ab893d5c8a1ae9a4558be48e14b0e605ee90d67.1411216924.git.segher@kernel.crashing.org> References: <8ab893d5c8a1ae9a4558be48e14b0e605ee90d67.1411216924.git.segher@kernel.crashing.org> In-Reply-To: <8ab893d5c8a1ae9a4558be48e14b0e605ee90d67.1411216924.git.segher@kernel.crashing.org> References: <8ab893d5c8a1ae9a4558be48e14b0e605ee90d67.1411216924.git.segher@kernel.crashing.org> X-IsSubscribed: yes Use a new code iterator to handle IOR, XOR. Also, we can now fold the AND patterns together with the boolean_or_operator patterns. 2014-09-20 Segher Boessenkool * config/rs6000/rs6000.md (iorxor): New code_iterator. (iorxor): New code_attr. (IORXOR): New code_attr. (*and3, *and3_dot, *and3_dot2): Delete. (ior3, xor3): Delete. (3): New. (splitter for "big" integer ior, xor): New. (*bool3): Move. Also handle AND. (*bool3_dot, *bool3_dot2): Also handle AND. (splitter for "big" integer ior, xor): Delete. --- gcc/config/rs6000/rs6000.md | 158 ++++++++++++-------------------------------- 1 file changed, 41 insertions(+), 117 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 0bb1a66..4d07269 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -437,6 +437,11 @@ (define_code_attr return_pred [(return "direct_return ()") (simple_return "1")]) (define_code_attr return_str [(return "") (simple_return "simple_")]) +; Logical operators. +(define_code_iterator iorxor [ior xor]) +(define_code_attr iorxor [(ior "ior") (xor "xor")]) +(define_code_attr IORXOR [(ior "IOR") (xor "XOR")]) + ; Signed/unsigned variants of ops. (define_code_iterator any_extend [sign_extend zero_extend]) (define_code_attr u [(sign_extend "") (zero_extend "u")]) @@ -2639,61 +2644,6 @@ (define_expand "and3" }) -(define_insn "*and3" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") - (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") - (match_operand:GPR 2 "gpc_reg_operand" "r")))] - "" - "and %0,%1,%2" - [(set_attr "type" "logical")]) - -(define_insn_and_split "*and3_dot" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") - (match_operand:GPR 2 "gpc_reg_operand" "r,r")) - (const_int 0))) - (clobber (match_scratch:GPR 0 "=r,r"))] - "mode == Pmode && rs6000_gen_cell_microcode" - "@ - and. %0,%1,%2 - #" - "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)" - [(set (match_dup 0) - (and:GPR (match_dup 1) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "" - [(set_attr "type" "logical") - (set_attr "dot" "yes") - (set_attr "length" "4,8")]) - -(define_insn_and_split "*and3_dot2" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") - (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") - (match_operand:GPR 2 "gpc_reg_operand" "r,r")) - (const_int 0))) - (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") - (and:GPR (match_dup 1) - (match_dup 2)))] - "mode == Pmode && rs6000_gen_cell_microcode" - "@ - and. %0,%1,%2 - #" - "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)" - [(set (match_dup 0) - (and:GPR (match_dup 1) - (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "" - [(set_attr "type" "logical") - (set_attr "dot" "yes") - (set_attr "length" "4,8")]) - - (define_insn "and3_imm" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r") @@ -2912,15 +2862,15 @@ (define_insn_and_split "*andsi3_internal6" [(set_attr "length" "8")]) -(define_expand "ior3" +(define_expand "3" [(set (match_operand:SDI 0 "gpc_reg_operand" "") - (ior:SDI (match_operand:SDI 1 "gpc_reg_operand" "") - (match_operand:SDI 2 "reg_or_cint_operand" "")))] + (iorxor:SDI (match_operand:SDI 1 "gpc_reg_operand" "") + (match_operand:SDI 2 "reg_or_cint_operand" "")))] "" { if (mode == DImode && !TARGET_POWERPC64) { - rs6000_split_logical (operands, IOR, false, false, false); + rs6000_split_logical (operands, , false, false, false); DONE; } @@ -2929,12 +2879,13 @@ (define_expand "ior3" rtx tmp = ((!can_create_pseudo_p () || rtx_equal_p (operands[0], operands[1])) ? operands[0] : gen_reg_rtx (mode)); - HOST_WIDE_INT value = INTVAL (operands[2]); - emit_insn (gen_ior3 (tmp, operands[1], - GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); + HOST_WIDE_INT value = INTVAL (operands[2]); + HOST_WIDE_INT lo = value & 0xffff; + HOST_WIDE_INT hi = value - lo; - emit_insn (gen_ior3 (operands[0], tmp, GEN_INT (value & 0xffff))); + emit_insn (gen_3 (tmp, operands[1], GEN_INT (hi))); + emit_insn (gen_3 (operands[0], tmp, GEN_INT (lo))); DONE; } @@ -2942,45 +2893,30 @@ (define_expand "ior3" operands[2] = force_reg (mode, operands[2]); }) -(define_expand "xor3" - [(set (match_operand:SDI 0 "gpc_reg_operand" "") - (xor:SDI (match_operand:SDI 1 "gpc_reg_operand" "") - (match_operand:SDI 2 "reg_or_cint_operand" "")))] +(define_split + [(set (match_operand:GPR 0 "gpc_reg_operand" "") + (iorxor:GPR (match_operand:GPR 1 "gpc_reg_operand" "") + (match_operand:GPR 2 "non_logical_cint_operand" "")))] "" + [(set (match_dup 3) + (iorxor:GPR (match_dup 1) + (match_dup 4))) + (set (match_dup 0) + (iorxor:GPR (match_dup 3) + (match_dup 5)))] { - if (mode == DImode && !TARGET_POWERPC64) - { - rs6000_split_logical (operands, XOR, false, false, false); - DONE; - } - - if (non_logical_cint_operand (operands[2], mode)) - { - rtx tmp = ((!can_create_pseudo_p () + operands[3] = ((!can_create_pseudo_p () || rtx_equal_p (operands[0], operands[1])) ? operands[0] : gen_reg_rtx (mode)); - HOST_WIDE_INT value = INTVAL (operands[2]); - - emit_insn (gen_xor3 (tmp, operands[1], - GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); - emit_insn (gen_xor3 (operands[0], tmp, GEN_INT (value & 0xffff))); - DONE; - } + HOST_WIDE_INT value = INTVAL (operands[2]); + HOST_WIDE_INT lo = value & 0xffff; + HOST_WIDE_INT hi = value - lo; - if (!reg_or_logical_cint_operand (operands[2], mode)) - operands[2] = force_reg (mode, operands[2]); + operands[4] = GEN_INT (hi); + operands[5] = GEN_INT (lo); }) -(define_insn "*bool3" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") - (match_operator:GPR 3 "boolean_or_operator" - [(match_operand:GPR 1 "gpc_reg_operand" "r") - (match_operand:GPR 2 "gpc_reg_operand" "r")]))] - "" - "%q3 %0,%1,%2" - [(set_attr "type" "logical")]) - (define_insn "*bool3_imm" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (match_operator:GPR 3 "boolean_or_operator" @@ -2990,9 +2926,18 @@ (define_insn "*bool3_imm" "%q3i%e2 %0,%1,%u2" [(set_attr "type" "logical")]) +(define_insn "*bool3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (match_operator:GPR 3 "boolean_operator" + [(match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:GPR 2 "gpc_reg_operand" "r")]))] + "" + "%q3 %0,%1,%2" + [(set_attr "type" "logical")]) + (define_insn_and_split "*bool3_dot" [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") - (compare:CC (match_operator:GPR 3 "boolean_or_operator" + (compare:CC (match_operator:GPR 3 "boolean_operator" [(match_operand:GPR 1 "gpc_reg_operand" "r,r") (match_operand:GPR 2 "gpc_reg_operand" "r,r")]) (const_int 0))) @@ -3014,7 +2959,7 @@ (define_insn_and_split "*bool3_dot" (define_insn_and_split "*bool3_dot2" [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") - (compare:CC (match_operator:GPR 3 "boolean_or_operator" + (compare:CC (match_operator:GPR 3 "boolean_operator" [(match_operand:GPR 1 "gpc_reg_operand" "r,r") (match_operand:GPR 2 "gpc_reg_operand" "r,r")]) (const_int 0))) @@ -3035,27 +2980,6 @@ (define_insn_and_split "*bool3_dot2" (set_attr "dot" "yes") (set_attr "length" "4,8")]) -;; Split a logical operation that we can't do in one insn into two insns, -;; each of which does one 16-bit part. This is used by combine. - -(define_split - [(set (match_operand:GPR 0 "gpc_reg_operand" "") - (match_operator:GPR 3 "boolean_or_operator" - [(match_operand:GPR 1 "gpc_reg_operand" "") - (match_operand:GPR 2 "non_logical_cint_operand" "")]))] - "" - [(set (match_dup 0) (match_dup 4)) - (set (match_dup 0) (match_dup 5))] -{ - rtx i; - i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); - operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), mode, - operands[1], i); - i = GEN_INT (INTVAL (operands[2]) & 0xffff); - operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), mode, - operands[0], i); -}) - (define_insn "*boolc3" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")