@@ -62,22 +62,21 @@
(match_operand:QI 2 "h8300_src_operand" "Y0,rn")))]
"register_operand (operands[0], QImode)
|| single_zero_operand (operands[2], QImode)"
- "#"
- "&& reload_completed"
+ "bclr %W2,%R0"
+ "&& reload_completed && !single_zero_operand (operands[2], QImode)"
[(parallel [(set (match_dup 0) (and:QI (match_dup 1) (match_dup 2)))
- (clobber (reg:CC CC_REG))])])
+ (clobber (reg:CC CC_REG))])]
+ ""
+ [(set_attr "length" "8,2")])
-(define_insn "andqi3_1_clobber_flags"
- [(set (match_operand:QI 0 "bit_operand" "=U,r")
- (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
- (match_operand:QI 2 "h8300_src_operand" "Y0,rn")))
+(define_insn "*andqi3_1<cczn>"
+ [(set (match_operand:QI 0 "register_operand" "=r")
+ (and:QI (match_operand:QI 1 "register_operand" "%0")
+ (match_operand:QI 2 "h8300_src_operand" "rn")))
(clobber (reg:CC CC_REG))]
- "register_operand (operands[0], QImode)
- || single_zero_operand (operands[2], QImode)"
- "@
- bclr %W2,%R0
- and %X2,%X0"
- [(set_attr "length" "2,8")])
+ ""
+ "and %X2,%X0"
+ [(set_attr "length" "2")])
(define_insn_and_split "*andor<mode>3"
[(set (match_operand:QHSI 0 "register_operand" "=r")
@@ -166,22 +165,14 @@
;; OR/XOR INSTRUCTIONS
;; ----------------------------------------------------------------------
-(define_insn "b<code>qi_msx"
- [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
- (ors:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
- (match_operand:QI 2 "single_one_operand" "Y2")))]
+(define_insn "b<code><mode>_msx"
+ [(set (match_operand:QHI 0 "bit_register_indirect_operand" "=WU")
+ (ors:QHI (match_operand:QHI 1 "bit_register_indirect_operand" "%0")
+ (match_operand:QHI 2 "single_one_operand" "Y2")))]
"TARGET_H8300SX && rtx_equal_p (operands[0], operands[1])"
{ return <CODE> == IOR ? "bset\\t%V2,%0" : "bnot\\t%V2,%0"; }
[(set_attr "length" "8")])
-(define_insn "b<code>hi_msx"
- [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
- (ors:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
- (match_operand:HI 2 "single_one_operand" "Y2")))]
- "TARGET_H8300SX"
- { return <CODE> == IOR ? "bset\\t%V2,%0" : "bnot\\t%V2,%0"; }
- [(set_attr "length" "8")])
-
(define_insn_and_split "<code>qi3_1"
[(set (match_operand:QI 0 "bit_operand" "=U,rQ")
(ors:QI (match_operand:QI 1 "bit_operand" "%0,0")
This is another minor patch for elimination of redundant test/compares on the H8. In particular it allows the compiler to use the result of a byte sized AND instruction to eliminate a compare/test. The only "trick" here is we have to distinguish between BCLR which clears a bit, but does not set condition codes and AND which does set condition codes. This patch also fixes a minor goof in the length computation of such instructions. The prior patterns had the length computation backwards. Byte sized ANDs are always 2 bytes while a BCLR can be from 2 to 8 bytes long depending on the target operand. Finally this patch also merges the H8SX BSET/BNOT for QI and HI mode. This is about 9 hours into the 22 hour test cycle (my timeouts are dramatically longer than the defaults to improve test coverage and stability). I'm not expecting any issues. Committed to the trunk, Jeff commit 941aa24ca9553b422dba6e267448ddd952bc52d1 Author: Jeff Law <jeffreyalaw@gmail.com> Date: Tue Jun 8 10:10:23 2021 -0400 Further improve redundant test/compare removal on the H8 gcc/ * config/h8300/logical.md (andqi3_1): Move BCLR case into define_insn_and_split. Create length attribute on define_insn_and_split. Only split for cases which we know will use AND. (andqi3_1<cczn>): Renamed from andqi3_1_clobber_flags. Only handle AND here and fix length computation. (b<code><mode>msx): Combine QImode and HImode H8/SX patterns using iterator.