diff --git a/gcc/config/rs6000/40x.md b/gcc/config/rs6000/40x.md
index b29e06a..0903536 100644
--- a/gcc/config/rs6000/40x.md
+++ b/gcc/config/rs6000/40x.md
@@ -36,8 +36,8 @@ (define_insn_reservation "ppc403-store" 2
   "iu_40x")
 
 (define_insn_reservation "ppc403-integer" 1
-  (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
-	    (and (eq_attr "type" "add,logical,shift")
+  (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
+	    (and (eq_attr "type" "add,logical,shift,exts")
 		 (eq_attr "dot" "no")))
        (eq_attr "cpu" "ppc403,ppc405"))
   "iu_40x")
@@ -54,7 +54,7 @@ (define_insn_reservation "ppc403-three" 1
 
 (define_insn_reservation "ppc403-compare" 3
   (and (ior (eq_attr "type" "cmp,compare")
-	    (and (eq_attr "type" "add,logical,shift")
+	    (and (eq_attr "type" "add,logical,shift,exts")
 		 (eq_attr "dot" "yes")))
        (eq_attr "cpu" "ppc403,ppc405"))
   "iu_40x,nothing,bpu_40x")
diff --git a/gcc/config/rs6000/440.md b/gcc/config/rs6000/440.md
index f956bd6..ff91fdb 100644
--- a/gcc/config/rs6000/440.md
+++ b/gcc/config/rs6000/440.md
@@ -53,8 +53,8 @@ (define_insn_reservation "ppc440-fpstore" 3
   "ppc440_issue,ppc440_l_pipe")
 
 (define_insn_reservation "ppc440-integer" 1
-  (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
-	    (and (eq_attr "type" "add,logical,shift")
+  (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
+	    (and (eq_attr "type" "add,logical,shift,exts")
 		 (eq_attr "dot" "no")))
        (eq_attr "cpu" "ppc440"))
   "ppc440_issue,ppc440_i_pipe|ppc440_j_pipe")
@@ -96,7 +96,7 @@ (define_insn_reservation "ppc440-branch" 1
 
 (define_insn_reservation "ppc440-compare" 2
   (and (ior (eq_attr "type" "cmp,compare,cr_logical,delayed_cr,mfcr")
-	    (and (eq_attr "type" "add,logical,shift")
+	    (and (eq_attr "type" "add,logical,shift,exts")
 		 (eq_attr "dot" "yes")))
        (eq_attr "cpu" "ppc440"))
   "ppc440_issue,ppc440_i_pipe")
diff --git a/gcc/config/rs6000/476.md b/gcc/config/rs6000/476.md
index 4c879f4..9bfd6b6 100644
--- a/gcc/config/rs6000/476.md
+++ b/gcc/config/rs6000/476.md
@@ -63,8 +63,8 @@ (define_insn_reservation "ppc476-fpstore" 4
    ppc476_lj_pipe")
 
 (define_insn_reservation "ppc476-simple-integer" 1
-  (and (ior (eq_attr "type" "integer,insert,exts")
-	    (and (eq_attr "type" "add,logical,shift")
+  (and (ior (eq_attr "type" "integer,insert")
+	    (and (eq_attr "type" "add,logical,shift,exts")
 		 (eq_attr "dot" "no")))
        (eq_attr "cpu" "ppc476"))
   "ppc476_issue,\
@@ -78,7 +78,7 @@ (define_insn_reservation "ppc476-complex-integer" 1
 
 (define_insn_reservation "ppc476-compare" 4
   (and (ior (eq_attr "type" "compare,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr")
-	    (and (eq_attr "type" "add,logical,shift")
+	    (and (eq_attr "type" "add,logical,shift,exts")
 		 (eq_attr "dot" "yes")))
        (eq_attr "cpu" "ppc476"))
   "ppc476_issue,\
diff --git a/gcc/config/rs6000/601.md b/gcc/config/rs6000/601.md
index e8207a8..de51cbf 100644
--- a/gcc/config/rs6000/601.md
+++ b/gcc/config/rs6000/601.md
@@ -45,8 +45,8 @@ (define_insn_reservation "ppc601-fpstore" 3
   "iu_ppc601+fpu_ppc601")
 
 (define_insn_reservation "ppc601-integer" 1
-  (and (ior (eq_attr "type" "integer,add,insert,trap,cntlz,exts,isel")
-	    (and (eq_attr "type" "shift")
+  (and (ior (eq_attr "type" "integer,add,insert,trap,cntlz,isel")
+	    (and (eq_attr "type" "shift,exts")
 		 (eq_attr "dot" "no")))
        (eq_attr "cpu" "ppc601"))
   "iu_ppc601")
@@ -75,7 +75,7 @@ (define_insn_reservation "ppc601-idiv" 36
 ; execute on the branch unit.
 (define_insn_reservation "ppc601-compare" 3
   (and (ior (eq_attr "type" "cmp,compare")
-	    (and (eq_attr "type" "shift")
+	    (and (eq_attr "type" "shift,exts")
 		 (eq_attr "dot" "yes")))
        (eq_attr "cpu" "ppc601"))
   "iu_ppc601,nothing,bpu_ppc601")
diff --git a/gcc/config/rs6000/603.md b/gcc/config/rs6000/603.md
index 871957a..dc03018 100644
--- a/gcc/config/rs6000/603.md
+++ b/gcc/config/rs6000/603.md
@@ -58,8 +58,8 @@ (define_insn_reservation "ppc603-storec" 8
   "lsu_603")
 
 (define_insn_reservation "ppc603-integer" 1
-  (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
-	    (and (eq_attr "type" "add,logical,shift")
+  (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
+	    (and (eq_attr "type" "add,logical,shift,exts")
 		 (eq_attr "dot" "no")))
        (eq_attr "cpu" "ppc603"))
   "iu_603")
@@ -94,7 +94,7 @@ (define_insn_reservation "ppc603-idiv" 37
 
 (define_insn_reservation "ppc603-compare" 3
   (and (ior (eq_attr "type" "cmp,compare")
-	    (and (eq_attr "type" "add,logical,shift")
+	    (and (eq_attr "type" "add,logical,shift,exts")
 		 (eq_attr "dot" "yes")))
        (eq_attr "cpu" "ppc603"))
   "iu_603,nothing,bpu_603")
diff --git a/gcc/config/rs6000/6xx.md b/gcc/config/rs6000/6xx.md
index 9d6ba05..db83469 100644
--- a/gcc/config/rs6000/6xx.md
+++ b/gcc/config/rs6000/6xx.md
@@ -73,8 +73,8 @@ (define_insn_reservation "ppc630-llsc" 4
   "lsu_6xx")
   
 (define_insn_reservation "ppc604-integer" 1
-  (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
-	    (and (eq_attr "type" "add,logical,shift")
+  (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
+	    (and (eq_attr "type" "add,logical,shift,exts")
 		 (eq_attr "dot" "no")))
        (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
   "iu1_6xx|iu2_6xx")
@@ -148,7 +148,7 @@ (define_insn_reservation "ppc620-ldiv" 37
 
 (define_insn_reservation "ppc604-compare" 3
   (and (ior (eq_attr "type" "cmp,compare")
-	    (and (eq_attr "type" "add,logical,shift")
+	    (and (eq_attr "type" "add,logical,shift,exts")
 		 (eq_attr "dot" "yes")))
        (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
   "(iu1_6xx|iu2_6xx)")
diff --git a/gcc/config/rs6000/7450.md b/gcc/config/rs6000/7450.md
index 4271efa..3679c79 100644
--- a/gcc/config/rs6000/7450.md
+++ b/gcc/config/rs6000/7450.md
@@ -73,8 +73,8 @@ (define_insn_reservation "ppc7450-sync" 35
   "ppc7450_du,lsu_7450")
 
 (define_insn_reservation "ppc7450-integer" 1
-  (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
-	    (and (eq_attr "type" "add,logical,shift")
+  (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
+	    (and (eq_attr "type" "add,logical,shift,exts")
 		 (eq_attr "dot" "no")))
        (eq_attr "cpu" "ppc7450"))
   "ppc7450_du,iu1_7450|iu2_7450|iu3_7450")
@@ -109,7 +109,7 @@ (define_insn_reservation "ppc7450-idiv" 23
 
 (define_insn_reservation "ppc7450-compare" 2
   (and (ior (eq_attr "type" "cmp,compare")
-	    (and (eq_attr "type" "add,logical,shift")
+	    (and (eq_attr "type" "add,logical,shift,exts")
 		 (eq_attr "dot" "yes")))
        (eq_attr "cpu" "ppc7450"))
   "ppc7450_du,(iu1_7450|iu2_7450|iu3_7450)")
diff --git a/gcc/config/rs6000/7xx.md b/gcc/config/rs6000/7xx.md
index aba4a77..b27fe35 100644
--- a/gcc/config/rs6000/7xx.md
+++ b/gcc/config/rs6000/7xx.md
@@ -61,8 +61,8 @@ (define_insn_reservation "ppc750-storec" 8
   "ppc750_du,lsu_7xx")
 
 (define_insn_reservation "ppc750-integer" 1
-  (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
-	    (and (eq_attr "type" "add,logical,shift")
+  (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
+	    (and (eq_attr "type" "add,logical,shift,exts")
 		 (eq_attr "dot" "no")))
        (eq_attr "cpu" "ppc750,ppc7400"))
   "ppc750_du,iu1_7xx|iu2_7xx")
@@ -102,7 +102,7 @@ (define_insn_reservation "ppc750-idiv" 19
 
 (define_insn_reservation "ppc750-compare" 2
   (and (ior (eq_attr "type" "cmp,compare")
-	    (and (eq_attr "type" "add,logical,shift")
+	    (and (eq_attr "type" "add,logical,shift,exts")
 		 (eq_attr "dot" "yes")))
        (eq_attr "cpu" "ppc750,ppc7400"))
   "ppc750_du,(iu1_7xx|iu2_7xx)")
diff --git a/gcc/config/rs6000/cell.md b/gcc/config/rs6000/cell.md
index b37cdba..f1ce352 100644
--- a/gcc/config/rs6000/cell.md
+++ b/gcc/config/rs6000/cell.md
@@ -166,8 +166,8 @@ (define_insn_reservation "cell-vecstore" 1
 
 ;; Integer latency is 2 cycles
 (define_insn_reservation "cell-integer" 2
-  (and (ior (eq_attr "type" "integer,trap,cntlz,exts,isel")
-	    (and (eq_attr "type" "add,logical,shift")
+  (and (ior (eq_attr "type" "integer,trap,cntlz,isel")
+	    (and (eq_attr "type" "add,logical,shift,exts")
 		 (eq_attr "dot" "no"))
 	    (and (eq_attr "type" "insert")
 		 (eq_attr "size" "64")))
@@ -202,7 +202,7 @@ (define_insn_reservation "cell-cmp" 1
 ;; add, addo, sub, subo, alter cr0, rldcli, rlwinm 
 (define_insn_reservation "cell-fast-cmp" 2
   (and (ior (eq_attr "type" "compare")
-	    (and (eq_attr "type" "add,logical,shift")
+	    (and (eq_attr "type" "add,logical,shift,exts")
 		 (eq_attr "dot" "yes")))
        (eq_attr "cpu" "cell")
        (eq_attr "cell_micro" "not"))
@@ -210,7 +210,7 @@ (define_insn_reservation "cell-fast-cmp" 2
 
 (define_insn_reservation "cell-cmp-microcoded" 9
   (and (ior (eq_attr "type" "compare")
-	    (and (eq_attr "type" "add,logical,shift")
+	    (and (eq_attr "type" "add,logical,shift,exts")
 		 (eq_attr "dot" "yes")))
        (eq_attr "cpu" "cell")
        (eq_attr "cell_micro" "always"))
diff --git a/gcc/config/rs6000/e300c2c3.md b/gcc/config/rs6000/e300c2c3.md
index f80ef30..276b9e9 100644
--- a/gcc/config/rs6000/e300c2c3.md
+++ b/gcc/config/rs6000/e300c2c3.md
@@ -84,7 +84,7 @@ (define_reservation "ppce300c3_iu_stage0"
 ;; Compares can be executed either one of the IU or SRU
 (define_insn_reservation "ppce300c3_cmp" 1
   (and (ior (eq_attr "type" "cmp,compare")
-	    (and (eq_attr "type" "add,logical,shift")
+	    (and (eq_attr "type" "add,logical,shift,exts")
 		 (eq_attr "dot" "yes")))
        (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
   "ppce300c3_decode,ppce300c3_issue+(ppce300c3_iu_stage0|ppce300c3_sru_stage0) \
@@ -93,7 +93,7 @@ (define_insn_reservation "ppce300c3_cmp" 1
 ;; Other one cycle IU insns
 (define_insn_reservation "ppce300c3_iu" 1
   (and (ior (eq_attr "type" "integer,insert,isel")
-	    (and (eq_attr "type" "add,logical,shift")
+	    (and (eq_attr "type" "add,logical,shift,exts")
 		 (eq_attr "dot" "no")))
        (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
   "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire")
diff --git a/gcc/config/rs6000/e500mc64.md b/gcc/config/rs6000/e500mc64.md
index 4582334..dc3eb6a 100644
--- a/gcc/config/rs6000/e500mc64.md
+++ b/gcc/config/rs6000/e500mc64.md
@@ -69,8 +69,8 @@ (define_reservation "e500mc64_su_stage0"
 
 ;; Simple SU insns.
 (define_insn_reservation "e500mc64_su" 1
-  (and (ior (eq_attr "type" "integer,insert,cntlz,exts")
-	    (and (eq_attr "type" "add,logical")
+  (and (ior (eq_attr "type" "integer,insert,cntlz")
+	    (and (eq_attr "type" "add,logical,exts")
 		 (eq_attr "dot" "no"))
 	    (and (eq_attr "type" "shift")
 		 (eq_attr "dot" "no")
@@ -80,7 +80,7 @@ (define_insn_reservation "e500mc64_su" 1
 
 (define_insn_reservation "e500mc64_su2" 2
   (and (ior (eq_attr "type" "cmp,compare,trap")
-	    (and (eq_attr "type" "add,logical")
+	    (and (eq_attr "type" "add,logical,exts")
 		 (eq_attr "dot" "yes"))
 	    (and (eq_attr "type" "shift")
 		 (eq_attr "dot" "yes")
diff --git a/gcc/config/rs6000/e5500.md b/gcc/config/rs6000/e5500.md
index 8d784e0..3cad8bd 100644
--- a/gcc/config/rs6000/e5500.md
+++ b/gcc/config/rs6000/e5500.md
@@ -56,8 +56,8 @@ (define_reservation "e5500_sfx"
 
 ;; SFX.
 (define_insn_reservation "e5500_sfx" 1
-  (and (ior (eq_attr "type" "integer,insert,cntlz,exts")
-	    (and (eq_attr "type" "add,logical")
+  (and (ior (eq_attr "type" "integer,insert,cntlz")
+	    (and (eq_attr "type" "add,logical,exts")
 		 (eq_attr "dot" "no"))
 	    (and (eq_attr "type" "shift")
 		 (eq_attr "var_shift" "no")))
@@ -66,7 +66,7 @@ (define_insn_reservation "e5500_sfx" 1
 
 (define_insn_reservation "e5500_sfx2" 2
   (and (ior (eq_attr "type" "cmp,compare,trap")
-	    (and (eq_attr "type" "add,logical")
+	    (and (eq_attr "type" "add,logical,exts")
 		 (eq_attr "dot"  "yes"))
 	    (and (eq_attr "type" "shift")
 		 (eq_attr "dot"  "yes")
diff --git a/gcc/config/rs6000/e6500.md b/gcc/config/rs6000/e6500.md
index a013a94..9d4b483 100644
--- a/gcc/config/rs6000/e6500.md
+++ b/gcc/config/rs6000/e6500.md
@@ -59,8 +59,8 @@ (define_reservation "e6500_sfx"
 
 ;; SFX.
 (define_insn_reservation "e6500_sfx" 1
-  (and (ior (eq_attr "type" "integer,insert,cntlz,exts")
-	    (and (eq_attr "type" "add,logical")
+  (and (ior (eq_attr "type" "integer,insert,cntlz")
+	    (and (eq_attr "type" "add,logical,exts")
 		 (eq_attr "dot"  "no"))
 	    (and (eq_attr "type" "shift")
 		 (eq_attr "dot"  "no")
@@ -70,7 +70,7 @@ (define_insn_reservation "e6500_sfx" 1
 
 (define_insn_reservation "e6500_sfx2" 2
   (and (ior (eq_attr "type" "cmp,compare,trap")
-	    (and (eq_attr "type" "add,logical")
+	    (and (eq_attr "type" "add,logical,exts")
 		 (eq_attr "dot"  "yes"))
 	    (and (eq_attr "type" "shift")
 		 (eq_attr "dot"  "yes")
diff --git a/gcc/config/rs6000/mpc.md b/gcc/config/rs6000/mpc.md
index 2f11a86..9ac611a 100644
--- a/gcc/config/rs6000/mpc.md
+++ b/gcc/config/rs6000/mpc.md
@@ -41,8 +41,8 @@ (define_insn_reservation "mpccore-fpload" 2
   "lsu_mpc")
 
 (define_insn_reservation "mpccore-integer" 1
-  (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
-	    (and (eq_attr "type" "add,logical,shift")
+  (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
+	    (and (eq_attr "type" "add,logical,shift,exts")
 		 (eq_attr "dot" "no")))
        (eq_attr "cpu" "mpccore"))
   "iu_mpc")
@@ -70,7 +70,7 @@ (define_insn_reservation "mpccore-idiv" 6
 
 (define_insn_reservation "mpccore-compare" 3
   (and (ior (eq_attr "type" "cmp,compare")
-	    (and (eq_attr "type" "add,logical,shift")
+	    (and (eq_attr "type" "add,logical,shift,exts")
 		 (eq_attr "dot" "yes")))
        (eq_attr "cpu" "mpccore"))
   "iu_mpc,nothing,bpu_mpc")
diff --git a/gcc/config/rs6000/power4.md b/gcc/config/rs6000/power4.md
index e46914e..a436ec7 100644
--- a/gcc/config/rs6000/power4.md
+++ b/gcc/config/rs6000/power4.md
@@ -210,8 +210,8 @@ (define_insn_reservation "power4-llsc" 11
 
 ; Integer latency is 2 cycles
 (define_insn_reservation "power4-integer" 2
-  (and (ior (eq_attr "type" "integer,trap,cntlz,exts,isel")
-	    (and (eq_attr "type" "add,logical,shift")
+  (and (ior (eq_attr "type" "integer,trap,cntlz,isel")
+	    (and (eq_attr "type" "add,logical,shift,exts")
 		 (eq_attr "dot" "no"))
 	    (and (eq_attr "type" "insert")
 		 (eq_attr "size" "64")))
@@ -258,7 +258,7 @@ (define_insn_reservation "power4-cmp" 3
 
 (define_insn_reservation "power4-compare" 2
   (and (ior (eq_attr "type" "compare")
-	    (and (eq_attr "type" "shift")
+	    (and (eq_attr "type" "shift,exts")
 		 (eq_attr "dot" "yes")))
        (eq_attr "cpu" "power4"))
   "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
diff --git a/gcc/config/rs6000/power5.md b/gcc/config/rs6000/power5.md
index 198db82..530c255 100644
--- a/gcc/config/rs6000/power5.md
+++ b/gcc/config/rs6000/power5.md
@@ -166,8 +166,8 @@ (define_insn_reservation "power5-llsc" 11
 
 ; Integer latency is 2 cycles
 (define_insn_reservation "power5-integer" 2
-  (and (ior (eq_attr "type" "integer,trap,cntlz,exts,isel,popcnt")
-	    (and (eq_attr "type" "add,logical,shift")
+  (and (ior (eq_attr "type" "integer,trap,cntlz,isel,popcnt")
+	    (and (eq_attr "type" "add,logical,shift,exts")
 		 (eq_attr "dot" "no"))
 	    (and (eq_attr "type" "insert")
 		 (eq_attr "size" "64")))
@@ -211,7 +211,7 @@ (define_insn_reservation "power5-cmp" 3
 
 (define_insn_reservation "power5-compare" 2
   (and (ior (eq_attr "type" "compare")
-	    (and (eq_attr "type" "shift")
+	    (and (eq_attr "type" "shift,exts")
 		 (eq_attr "dot" "yes")))
        (eq_attr "cpu" "power5"))
   "du1_power5+du2_power5,iu1_power5,iu2_power5")
diff --git a/gcc/config/rs6000/power6.md b/gcc/config/rs6000/power6.md
index e4a82a2..695f642 100644
--- a/gcc/config/rs6000/power6.md
+++ b/gcc/config/rs6000/power6.md
@@ -235,6 +235,7 @@ (define_insn_reservation "power6-isel" 1
 
 (define_insn_reservation "power6-exts" 1
   (and (eq_attr "type" "exts")
+       (eq_attr "dot" "no")
        (eq_attr "cpu" "power6"))
   "FXU_power6")
 
@@ -333,7 +334,9 @@ (define_insn_reservation "power6-cmp" 1
   "FXU_power6")
 
 (define_insn_reservation "power6-compare" 1
-  (and (eq_attr "type" "compare")
+  (and (ior (eq_attr "type" "compare")
+            (and (eq_attr "type" "exts")
+                 (eq_attr "dot" "yes")))
        (eq_attr "cpu" "power6"))
   "FXU_power6")
 
diff --git a/gcc/config/rs6000/power7.md b/gcc/config/rs6000/power7.md
index b2a0caf..8be2879 100644
--- a/gcc/config/rs6000/power7.md
+++ b/gcc/config/rs6000/power7.md
@@ -174,8 +174,8 @@ (define_insn_reservation "power7-sync" 11
 
 ; FX Unit
 (define_insn_reservation "power7-integer" 1
-  (and (ior (eq_attr "type" "integer,insert,trap,exts,isel,popcnt")
-	    (and (eq_attr "type" "add,logical,shift")
+  (and (ior (eq_attr "type" "integer,insert,trap,isel,popcnt")
+	    (and (eq_attr "type" "add,logical,shift,exts")
 		 (eq_attr "dot" "no")))
        (eq_attr "cpu" "power7"))
   "DU_power7,FXU_power7")
@@ -204,7 +204,7 @@ (define_insn_reservation "power7-cmp" 1
 
 (define_insn_reservation "power7-compare" 2
   (and (ior (eq_attr "type" "compare")
-	    (and (eq_attr "type" "shift")
+	    (and (eq_attr "type" "shift,exts")
 		 (eq_attr "dot" "yes")))
        (eq_attr "cpu" "power7"))
   "DU2F_power7,FXU_power7,FXU_power7")
diff --git a/gcc/config/rs6000/power8.md b/gcc/config/rs6000/power8.md
index c7c0aa9..4b03ac2 100644
--- a/gcc/config/rs6000/power8.md
+++ b/gcc/config/rs6000/power8.md
@@ -168,8 +168,8 @@ (define_insn_reservation "power8-sync" 1
 
 ; FX Unit
 (define_insn_reservation "power8-1cyc" 1
-  (and (ior (eq_attr "type" "integer,insert,trap,exts,isel")
-	    (and (eq_attr "type" "add,logical,shift")
+  (and (ior (eq_attr "type" "integer,insert,trap,isel")
+	    (and (eq_attr "type" "add,logical,shift,exts")
 		 (eq_attr "dot" "no")))
        (eq_attr "cpu" "power8"))
   "DU_any_power8,FXU_power8")
@@ -216,7 +216,7 @@ (define_insn_reservation "power8-fast-compare" 2
 ; shift with dot : rlwinm./slwi./rlwnm./slw./etc
 (define_insn_reservation "power8-compare" 2
   (and (ior (eq_attr "type" "compare")
-	    (and (eq_attr "type" "shift")
+	    (and (eq_attr "type" "shift,exts")
 		 (eq_attr "dot" "yes")))
        (eq_attr "cpu" "power8"))
   "DU_cracked_power8,FXU_power8,FXU_power8")
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 0c5b996..ef7bc69 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -1022,6 +1022,9 @@ (define_predicate "lwa_operand"
     return true;
   if (!memory_operand (inner, mode))
     return false;
+  if (!rs6000_gen_cell_microcode)
+    return false;
+
   addr = XEXP (inner, 0);
   if (GET_CODE (addr) == PRE_INC
       || GET_CODE (addr) == PRE_DEC
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index d13e71e..5b1aa55 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -26444,6 +26444,7 @@ rs6000_adjust_cost (rtx_insn *insn, rtx link, rtx_insn *dep_insn, int cost)
                 case TYPE_CR_LOGICAL:
                 case TYPE_DELAYED_CR:
 		  return cost + 2;
+                case TYPE_EXTS:
                 case TYPE_MUL:
 		  if (get_attr_dot (dep_insn) == DOT_YES)
 		    return cost + 2;
@@ -26736,6 +26737,8 @@ is_cracked_insn (rtx insn)
 	      && get_attr_update (insn) == UPDATE_YES)
 	  || type == TYPE_DELAYED_CR
 	  || type == TYPE_COMPARE
+	  || (type == TYPE_EXTS
+	      && get_attr_dot (insn) == DOT_YES)
 	  || (type == TYPE_SHIFT
 	      && get_attr_dot (insn) == DOT_YES
 	      && get_attr_var_shift (insn) == VAR_SHIFT_NO)
@@ -27624,6 +27627,7 @@ insn_must_be_first_in_group (rtx insn)
           return true;
         case TYPE_MUL:
         case TYPE_SHIFT:
+        case TYPE_EXTS:
           if (get_attr_dot (insn) == DOT_YES)
             return true;
           else
@@ -27665,6 +27669,7 @@ insn_must_be_first_in_group (rtx insn)
         case TYPE_MTJMPR:
           return true;
         case TYPE_SHIFT:
+        case TYPE_EXTS:
         case TYPE_MUL:
           if (get_attr_dot (insn) == DOT_YES)
             return true;
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 6cd6404..d2bc07d 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -181,7 +181,7 @@ (define_attr "type"
 (define_attr "size" "8,16,32,64" (const_string "32"))
 
 ;; Is this instruction record form ("dot", signed compare to 0, writing CR0)?
-;; This is used for add, logical, shift, mul.
+;; This is used for add, logical, shift, exts, mul.
 (define_attr "dot" "no,yes" (const_string "no"))
 
 ;; Does this instruction sign-extend its result?
@@ -254,7 +254,7 @@ (define_attr "cpu"
 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
 (define_attr "cell_micro" "not,conditional,always"
   (if_then_else (ior (eq_attr "type" "compare")
-		     (and (eq_attr "type" "shift,mul")
+		     (and (eq_attr "type" "shift,exts,mul")
 			  (eq_attr "dot" "yes"))
 		     (and (eq_attr "type" "load")
 			  (eq_attr "sign_extend" "yes"))
@@ -726,150 +726,124 @@ (define_insn_and_split "*zero_extendsi<mode>2_dot2"
    (set_attr "length" "4,8")])
 
 
-(define_insn "extendqidi2"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
-  "TARGET_POWERPC64"
+(define_insn "extendqi<mode>2"
+  [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r")
+	(sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r")))]
+  ""
   "extsb %0,%1"
   [(set_attr "type" "exts")])
 
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
+(define_insn_and_split "*extendqi<mode>2_dot"
+  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
+	(compare:CC (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
 		    (const_int 0)))
-   (clobber (match_scratch:DI 2 "=r,r"))]
-  "TARGET_64BIT"
+   (clobber (match_scratch:EXTQI 0 "=r,r"))]
+  "rs6000_gen_cell_microcode"
   "@
-   extsb. %2,%1
+   extsb. %0,%1
    #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
-	(compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 2 ""))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 2)
-	(sign_extend:DI (match_dup 1)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 2)
+  "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
+  [(set (match_dup 0)
+	(sign_extend:EXTQI (match_dup 1)))
+   (set (match_dup 2)
+	(compare:CC (match_dup 0)
 		    (const_int 0)))]
-  "")
+  ""
+  [(set_attr "type" "exts")
+   (set_attr "dot" "yes")
+   (set_attr "length" "4,8")])
 
-(define_insn ""
+(define_insn_and_split "*extendqi<mode>2_dot2"
   [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-	(compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
+	(compare:CC (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
 		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(sign_extend:DI (match_dup 1)))]
-  "TARGET_64BIT"
+   (set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
+	(sign_extend:EXTQI (match_dup 1)))]
+  "rs6000_gen_cell_microcode"
   "@
    extsb. %0,%1
    #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
-	(compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(sign_extend:DI (match_dup 1)))]
-  "TARGET_POWERPC64 && reload_completed"
+  "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
   [(set (match_dup 0)
-	(sign_extend:DI (match_dup 1)))
+	(sign_extend:EXTQI (match_dup 1)))
    (set (match_dup 2)
 	(compare:CC (match_dup 0)
 		    (const_int 0)))]
-  "")
+  ""
+  [(set_attr "type" "exts")
+   (set_attr "dot" "yes")
+   (set_attr "length" "4,8")])
 
-(define_expand "extendhidi2"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
-  "TARGET_POWERPC64"
+
+(define_expand "extendhi<mode>2"
+  [(set (match_operand:EXTHI 0 "gpc_reg_operand" "")
+	(sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "")))]
+  ""
   "")
 
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
-  "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
+(define_insn "*extendhi<mode>2"
+  [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
+	(sign_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
+  "rs6000_gen_cell_microcode"
   "@
    lha%U1%X1 %0,%1
    extsh %0,%1"
   [(set_attr "type" "load,exts")
    (set_attr "sign_extend" "yes")])
 
-(define_insn ""
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
-  "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
+(define_insn "*extendhi<mode>2_noload"
+  [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r")
+        (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r")))]
+  "!rs6000_gen_cell_microcode"
   "extsh %0,%1"
   [(set_attr "type" "exts")])
 
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
+(define_insn_and_split "*extendhi<mode>2_dot"
+  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
+	(compare:CC (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
 		    (const_int 0)))
-   (clobber (match_scratch:DI 2 "=r,r"))]
-  "TARGET_64BIT"
+   (clobber (match_scratch:EXTHI 0 "=r,r"))]
+  "rs6000_gen_cell_microcode"
   "@
-   extsh. %2,%1
+   extsh. %0,%1
    #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
-	(compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 2 ""))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 2)
-	(sign_extend:DI (match_dup 1)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 2)
+  "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
+  [(set (match_dup 0)
+	(sign_extend:EXTHI (match_dup 1)))
+   (set (match_dup 2)
+	(compare:CC (match_dup 0)
 		    (const_int 0)))]
-  "")
+  ""
+  [(set_attr "type" "exts")
+   (set_attr "dot" "yes")
+   (set_attr "length" "4,8")])
 
-(define_insn ""
+(define_insn_and_split "*extendhi<mode>2_dot2"
   [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-	(compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
+	(compare:CC (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
 		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(sign_extend:DI (match_dup 1)))]
-  "TARGET_64BIT"
+   (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
+	(sign_extend:EXTHI (match_dup 1)))]
+  "rs6000_gen_cell_microcode"
   "@
    extsh. %0,%1
    #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
-	(compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(sign_extend:DI (match_dup 1)))]
-  "TARGET_POWERPC64 && reload_completed"
+  "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
   [(set (match_dup 0)
-	(sign_extend:DI (match_dup 1)))
+	(sign_extend:EXTHI (match_dup 1)))
    (set (match_dup 2)
 	(compare:CC (match_dup 0)
 		    (const_int 0)))]
-  "")
+  ""
+  [(set_attr "type" "exts")
+   (set_attr "dot" "yes")
+   (set_attr "length" "4,8")])
 
-(define_expand "extendsidi2"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
-  "TARGET_POWERPC64"
-  "")
 
-(define_insn "*extendsidi2_lfiwax"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wj,!wl,!wu")
-	(sign_extend:DI (match_operand:SI 1 "lwa_operand" "Y,r,r,Z,Z")))]
-  "TARGET_POWERPC64 && TARGET_LFIWAX"
+(define_insn "extendsi<mode>2"
+  [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,??wj,!wl,!wu")
+	(sign_extend:EXTSI (match_operand:SI 1 "lwa_operand" "Y,r,r,Z,Z")))]
+  ""
   "@
    lwa%U1%X1 %0,%1
    extsw %0,%1
@@ -879,270 +853,46 @@ (define_insn "*extendsidi2_lfiwax"
   [(set_attr "type" "load,exts,mffgpr,fpload,fpload")
    (set_attr "sign_extend" "yes")])
 
-(define_insn "*extendsidi2_nocell"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(sign_extend:DI (match_operand:SI 1 "lwa_operand" "Y,r")))]
-  "TARGET_POWERPC64 && rs6000_gen_cell_microcode && !TARGET_LFIWAX"
-  "@
-   lwa%U1%X1 %0,%1
-   extsw %0,%1"
-  [(set_attr "type" "load,exts")
-   (set_attr "sign_extend" "yes")])
-
-(define_insn "*extendsidi2_nocell"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
-  "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
-  "extsw %0,%1"
-  [(set_attr "type" "exts")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 2 "=r,r"))]
-  "TARGET_64BIT"
-  "@
-   extsw. %2,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
-	(compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 2 ""))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 2)
-	(sign_extend:DI (match_dup 1)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 2)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
+(define_insn_and_split "*extendsi<mode>2_dot"
   [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-	(compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
+	(compare:CC (sign_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
 		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(sign_extend:DI (match_dup 1)))]
-  "TARGET_64BIT"
+   (clobber (match_scratch:EXTSI 0 "=r,r"))]
+  "rs6000_gen_cell_microcode"
   "@
    extsw. %0,%1
    #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
-	(compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(sign_extend:DI (match_dup 1)))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 0)
-	(sign_extend:DI (match_dup 1)))
-   (set (match_dup 2)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
-
-(define_insn "extendqisi2"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
-  ""
-  "extsb %0,%1"
-  [(set_attr "type" "exts")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 2 "=r,r"))]
-  ""
-  "@
-   extsb. %2,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
-	(compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 2 ""))]
-  "reload_completed"
-  [(set (match_dup 2)
-	(sign_extend:SI (match_dup 1)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 2)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-	(compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(sign_extend:SI (match_dup 1)))]
-  ""
-  "@
-   extsb. %0,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
-	(compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(sign_extend:SI (match_dup 1)))]
-  "reload_completed"
+  "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
   [(set (match_dup 0)
-	(sign_extend:SI (match_dup 1)))
+	(sign_extend:EXTSI (match_dup 1)))
    (set (match_dup 2)
 	(compare:CC (match_dup 0)
 		    (const_int 0)))]
-  "")
-
-
-(define_insn "extendqihi2"
-  [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
-	(sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
-  ""
-  "extsb %0,%1"
-  [(set_attr "type" "exts")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:HI 2 "=r,r"))]
   ""
-  "@
-   extsb. %2,%1
-   #"
-  [(set_attr "type" "compare")
+  [(set_attr "type" "exts")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
-	(compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:HI 2 ""))]
-  "reload_completed"
-  [(set (match_dup 2)
-	(sign_extend:HI (match_dup 1)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 2)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
+(define_insn_and_split "*extendsi<mode>2_dot2"
   [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-	(compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
+	(compare:CC (sign_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
 		    (const_int 0)))
-   (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
-	(sign_extend:HI (match_dup 1)))]
-  ""
+   (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r")
+	(sign_extend:EXTSI (match_dup 1)))]
+  "rs6000_gen_cell_microcode"
   "@
-   extsb. %0,%1
+   extsw. %0,%1
    #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
-	(compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:HI 0 "gpc_reg_operand" "")
-	(sign_extend:HI (match_dup 1)))]
-  "reload_completed"
+  "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
   [(set (match_dup 0)
-	(sign_extend:HI (match_dup 1)))
+	(sign_extend:EXTSI (match_dup 1)))
    (set (match_dup 2)
 	(compare:CC (match_dup 0)
 		    (const_int 0)))]
-  "")
-
-
-(define_expand "extendhisi2"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-	(sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
-  ""
-  "")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
-  "rs6000_gen_cell_microcode"
-  "@
-   lha%U1%X1 %0,%1
-   extsh %0,%1"
-  [(set_attr "type" "load,exts")
-   (set_attr "sign_extend" "yes")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-        (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
-  "!rs6000_gen_cell_microcode"
-  "extsh %0,%1"
-  [(set_attr "type" "exts")])
-
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-	(compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 2 "=r,r"))]
   ""
-  "@
-   extsh. %2,%1
-   #"
-  [(set_attr "type" "compare")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
-	(compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 2 ""))]
-  "reload_completed"
-  [(set (match_dup 2)
-	(sign_extend:SI (match_dup 1)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 2)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
-  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-	(compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(sign_extend:SI (match_dup 1)))]
-  ""
-  "@
-   extsh. %0,%1
-   #"
-  [(set_attr "type" "compare")
+  [(set_attr "type" "exts")
+   (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
-	(compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(sign_extend:SI (match_dup 1)))]
-  "reload_completed"
-  [(set (match_dup 0)
-	(sign_extend:SI (match_dup 1)))
-   (set (match_dup 2)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
 
 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
 
diff --git a/gcc/config/rs6000/rs64.md b/gcc/config/rs6000/rs64.md
index c891ac4..8925f38 100644
--- a/gcc/config/rs6000/rs64.md
+++ b/gcc/config/rs6000/rs64.md
@@ -46,8 +46,8 @@ (define_insn_reservation "rs64a-llsc" 2
   "lsu_rs64")
 
 (define_insn_reservation "rs64a-integer" 1
-  (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
-	    (and (eq_attr "type" "add,logical,shift")
+  (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
+	    (and (eq_attr "type" "add,logical,shift,exts")
 		 (eq_attr "dot" "no")))
        (eq_attr "cpu" "rs64a"))
   "iu_rs64")
@@ -100,7 +100,7 @@ (define_insn_reservation "rs64a-ldiv" 66
 
 (define_insn_reservation "rs64a-compare" 3
   (and (ior (eq_attr "type" "cmp,compare")
-	    (and (eq_attr "type" "add,logical,shift")
+	    (and (eq_attr "type" "add,logical,shift,exts")
 		 (eq_attr "dot" "yes")))
        (eq_attr "cpu" "rs64a"))
   "iu_rs64,nothing,bpu_rs64")
