Index: gcc/ChangeLog
===================================================================
--- gcc/ChangeLog	(revision 255468)
+++ gcc/ChangeLog	(working copy)
@@ -1,3 +1,8 @@
+2017-12-07  Sebastian Perta  <sebastian.perta@renesas.com>
+
+	* config/rl78/rl78.md: New define_expand "smindi3".
+	
+
 2017-12-07  Tamar Christina  <tamar.christina@arm.com>
 
 	PR target/82641
Index: gcc/config/rl78/rl78.md
===================================================================
--- gcc/config/rl78/rl78.md	(revision 255468)
+++ gcc/config/rl78/rl78.md	(working copy)
@@ -718,3 +718,13 @@
   [(set_attr "valloc" "macax")
    (set_attr "is_g13_muldiv_insn" "yes")]
 )
+
+(define_expand "smindi3"
+ [(set (match_operand:DI          0 "nonimmediate_operand" "")
+	(smin:DI (match_operand:DI 1 "general_operand"      "")
+		 (match_operand:DI    2 "general_operand"      "")))
+   ]
+  "optimize_size"
+  "rl78_emit_libcall (\"__smindi3\", SMIN, DImode, DImode, 3, operands);
+   DONE;"
+)
Index: libgcc/ChangeLog
===================================================================
--- libgcc/ChangeLog	(revision 255468)
+++ libgcc/ChangeLog	(working copy)
@@ -1,3 +1,8 @@
+2017-12-07  Sebastian Perta  <sebastian.perta@renesas.com>
+ 
+	* config/rl78/smindi3.S: New assembly file.
+	* config/rl78/t-rl78: Added smindi3.S to LIB2ADD.
+
 2017-11-30  Michael Meissner  <meissner@linux.vnet.ibm.com>
 
 	* config/rs6000/_mulkc3.c (__mulkc3): Add forward declaration.
Index: libgcc/config/rl78/t-rl78
===================================================================
--- libgcc/config/rl78/t-rl78	(revision 255468)
+++ libgcc/config/rl78/t-rl78	(working copy)
@@ -32,7 +32,8 @@
 	$(srcdir)/config/rl78/fpmath-sf.S \
 	$(srcdir)/config/rl78/cmpsi2.S \
 	$(srcdir)/config/rl78/adddi3.S \
-	$(srcdir)/config/rl78/subdi3.S
+	$(srcdir)/config/rl78/subdi3.S \
+	$(srcdir)/config/rl78/smindi3.S
 
 LIB2FUNCS_EXCLUDE = _clzhi2 _clzsi2 _ctzhi2 _ctzsi2 \
   _popcounthi2 _popcountsi2 \
Index: libgcc/config/rl78/smindi3.S
===================================================================
--- libgcc/config/rl78/smindi3.S	(nonexistent)
+++ libgcc/config/rl78/smindi3.S	(working copy)
@@ -0,0 +1,76 @@
+;   Copyright (C) 2017 Free Software Foundation, Inc.
+;   Contributed by Sebastian Perta.
+; 
+; This file is free software; you can redistribute it and/or modify it
+; under the terms of the GNU General Public License as published by the
+; Free Software Foundation; either version 3, or (at your option) any
+; later version.
+; 
+; This file is distributed in the hope that it will be useful, but
+; WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+; General Public License for more details.
+; 
+; Under Section 7 of GPL version 3, you are granted additional
+; permissions described in the GCC Runtime Library Exception, version
+; 3.1, as published by the Free Software Foundation.
+;
+; You should have received a copy of the GNU General Public License and
+; a copy of the GCC Runtime Library Exception along with this program;
+; see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+; <http://www.gnu.org/licenses/>.
+
+
+#include "vregs.h"
+
+    .text
+
+START_FUNC ___smindi3
+
+    ; copy first argument/operand to the output registers
+    movw   ax, [sp+4]
+    movw   r8, ax
+    movw   ax, [sp+6]
+    movw   r10, ax
+    movw   ax, [sp+8]
+    movw   r12, ax
+    movw   ax, [sp+10]
+    movw   r14, ax
+
+    ; use 16-bit compares from the most significant words downto the least
significant ones
+    movw   ax, [sp+18]
+    cmpw   ax, r14
+    xor1   CY, a.7   ; first compare accounts for the
+    xor1   CY, r15.7 ; sign bits of the two operands
+    bc     $.L1
+    bnz    $.L2
+
+    movw   ax, [sp+16]
+    cmpw   ax, r12
+    bc     $.L1
+    bnz    $.L2
+
+    movw   ax, [sp+14]
+    cmpw   ax, r10
+    bc     $.L1
+    bnz    $.L2
+
+    movw   ax, [sp+12]
+    cmpw   ax, r8
+    bc     $.L1
+    ret
+
+.L1:
+    ; copy second argument/operand to the output registers
+    movw   ax, [sp+12]
+    movw   r8, ax
+    movw   ax, [sp+14]
+    movw   r10, ax
+    movw   ax, [sp+16]
+    movw   r12, ax
+    movw   ax, [sp+18]
+    movw   r14, ax
+.L2:
+    ret
+
