From patchwork Mon Mar 2 01:44:47 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Terry Guo X-Patchwork-Id: 444896 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 89AC01400A0 for ; Mon, 2 Mar 2015 12:45:16 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass reason="1024-bit key; unprotected key" header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=k022gePz; dkim-adsp=none (unprotected policy); dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; q=dns; s=default; b=VmbSeSDJrjD74F0MZ624YqvsvE4Sd8PR8VcRllK1XiIK7+L67O CipHv+EJ7j1PyDlgNRMkg7VtFcewbXoNLTE8qBhCmIQbfeVikakDFNBs+5VnAJ3p kqQ/h3TwNU59FLPUp3avfdQCx3d05Mdleywv5+KOFe9Hr+HgUkZwCeHdc= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; s= default; bh=gKhZzELNFcUHFfQxiNHu8PTNE4o=; b=k022gePzriB9l9v6hPyd JjVPNxBxXzySyAKz+6MWV7P6mvheJUm99avKUlUqAE9o+9TtLiUlBCGoajX4KO8q 7EfIHLlvbhDOdRA9nLNIiinM1WbK80XWNyBc+1kXmAvd/k9++Nl9uvuRrVH4Jvk5 YLUlvAoSmFuAR/q1MVhPVIc= Received: (qmail 68106 invoked by alias); 2 Mar 2015 01:45:04 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 68029 invoked by uid 89); 2 Mar 2015 01:45:01 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 02 Mar 2015 01:44:58 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by service87.mimecast.com; Mon, 02 Mar 2015 01:44:55 +0000 Received: from shawin252 ([10.164.6.104]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 2 Mar 2015 01:44:54 +0000 From: "Terry Guo" To: Cc: "Ramana Radhakrishnan" , "Richard Earnshaw" Subject: [PATCH][ARM]Automatically add -mthumb for thumb-only target when mode isn't specified Date: Mon, 2 Mar 2015 09:44:47 +0800 Message-ID: <000001d0548a$789a1bd0$69ce5370$@arm.com> MIME-Version: 1.0 X-MC-Unique: 115030201445500201 X-IsSubscribed: yes Hi there, If target mode isn't specified via either gcc configuration option --with-mode or command line, this patch intends to improve gcc driver to automatically add option -mthumb for thumb-only target. Tested with gcc regression test for various arm targets, no regression. Is it OK? BR, Terry gcc/ChangeLog: 2015-03-02 Terry Guo * common/config/arm/arm-common.c (arm_is_target_thumb_only): New function. * config/arm/arm-protos.h (FL_ Macros): Move to ... * config/arm/arm-opts.h (FL_ Macros): ... here. (struct arm_arch_core_flag): New struct. (arm_arch_core_flags): New array for arch/core and flag map. * config/arm/arm.h (MODE_SET_SPEC_FUNCTIONS): Define new SPEC function. (EXTRA_SPEC_FUNCTIONS): Include new SPEC function. (MODE_SET_SPECS): New SPEC. (DRIVER_SELF_SPECS): Include new SPEC. diff --git a/gcc/common/config/arm/arm-common.c b/gcc/common/config/arm/arm-common.c index 86673b7..e17ee03 100644 --- a/gcc/common/config/arm/arm-common.c +++ b/gcc/common/config/arm/arm-common.c @@ -97,6 +97,28 @@ arm_rewrite_mcpu (int argc, const char **argv) return arm_rewrite_selected_cpu (argv[argc - 1]); } +/* Called by driver to check whether the target denoted by current + command line options is thumb-only target. If -march present, + check the last -march option. If no -march, check the last -mcpu + option. */ +const char * +arm_is_target_thumb_only (int argc, const char **argv) +{ + unsigned int opt; + + if (argc) + { + for (opt = 0; opt < (ARRAY_SIZE (arm_arch_core_flags) - 1); opt++) + if ((strcmp (argv[argc - 1], arm_arch_core_flags[opt].name) == 0) + && ((arm_arch_core_flags[opt].flags & FL_NOTM) == 0)) + return "-mthumb"; + + return NULL; + } + else + return NULL; +} + #undef ARM_CPU_NAME_LENGTH diff --git a/gcc/config/arm/arm-opts.h b/gcc/config/arm/arm-opts.h index 039e333..222d20e 100644 --- a/gcc/config/arm/arm-opts.h +++ b/gcc/config/arm/arm-opts.h @@ -77,4 +77,93 @@ enum arm_tls_type { TLS_GNU, TLS_GNU2 }; + +/* Flags used to identify the presence of processor capabilities. */ + +/* Bit values used to identify processor capabilities. */ +#define FL_CO_PROC (1 << 0) /* Has external co-processor bus */ +#define FL_ARCH3M (1 << 1) /* Extended multiply */ +#define FL_MODE26 (1 << 2) /* 26-bit mode support */ +#define FL_MODE32 (1 << 3) /* 32-bit mode support */ +#define FL_ARCH4 (1 << 4) /* Architecture rel 4 */ +#define FL_ARCH5 (1 << 5) /* Architecture rel 5 */ +#define FL_THUMB (1 << 6) /* Thumb aware */ +#define FL_LDSCHED (1 << 7) /* Load scheduling necessary */ +#define FL_STRONG (1 << 8) /* StrongARM */ +#define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */ +#define FL_XSCALE (1 << 10) /* XScale */ +/* spare (1 << 11) */ +#define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds + media instructions. */ +#define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */ +#define FL_WBUF (1 << 14) /* Schedule for write buffer ops. + Note: ARM6 & 7 derivatives only. */ +#define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */ +#define FL_THUMB2 (1 << 16) /* Thumb-2. */ +#define FL_NOTM (1 << 17) /* Instructions not present in the 'M' + profile. */ +#define FL_THUMB_DIV (1 << 18) /* Hardware divide (Thumb mode). */ +#define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */ +#define FL_NEON (1 << 20) /* Neon instructions. */ +#define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M + architecture. */ +#define FL_ARCH7 (1 << 22) /* Architecture 7. */ +#define FL_ARM_DIV (1 << 23) /* Hardware divide (ARM mode). */ +#define FL_ARCH8 (1 << 24) /* Architecture 8. */ +#define FL_CRC32 (1 << 25) /* ARMv8 CRC32 instructions. */ + +#define FL_SMALLMUL (1 << 26) /* Small multiply supported. */ + +#define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ +#define FL_IWMMXT2 (1 << 30) /* "Intel Wireless MMX2 technology". */ + +/* Flags that only effect tuning, not available instructions. */ +#define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \ + | FL_CO_PROC) + +#define FL_FOR_ARCH2 FL_NOTM +#define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32) +#define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M) +#define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4) +#define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB) +#define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5) +#define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB) +#define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E) +#define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB) +#define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE +#define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6) +#define FL_FOR_ARCH6J FL_FOR_ARCH6 +#define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K) +#define FL_FOR_ARCH6Z FL_FOR_ARCH6 +#define FL_FOR_ARCH6ZK FL_FOR_ARCH6K +#define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2) +#define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM) +#define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7) +#define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K) +#define FL_FOR_ARCH7VE (FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV) +#define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_THUMB_DIV) +#define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV) +#define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM) +#define FL_FOR_ARCH8A (FL_FOR_ARCH7VE | FL_ARCH8) + +struct arm_arch_core_flag +{ + const char *const name; + const unsigned long flags; +}; + +static const struct arm_arch_core_flag arm_arch_core_flags[] = +{ +#undef ARM_CORE +#define ARM_CORE(NAME, X, IDENT, ARCH, FLAGS, COSTS) \ + {NAME, FLAGS | FL_FOR_ARCH##ARCH}, +#include "arm-cores.def" +#undef ARM_CORE +#undef ARM_ARCH +#define ARM_ARCH(NAME, CORE, ARCH, FLAGS) \ + {NAME, FLAGS}, +#include "arm-arches.def" +#undef ARM_ARCH + {NULL, 0} +}; #endif diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 307babb..ebb341b 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -325,74 +325,6 @@ extern const char *arm_rewrite_selected_cpu (const char *name); extern bool arm_is_constant_pool_ref (rtx); -/* Flags used to identify the presence of processor capabilities. */ - -/* Bit values used to identify processor capabilities. */ -#define FL_CO_PROC (1 << 0) /* Has external co-processor bus */ -#define FL_ARCH3M (1 << 1) /* Extended multiply */ -#define FL_MODE26 (1 << 2) /* 26-bit mode support */ -#define FL_MODE32 (1 << 3) /* 32-bit mode support */ -#define FL_ARCH4 (1 << 4) /* Architecture rel 4 */ -#define FL_ARCH5 (1 << 5) /* Architecture rel 5 */ -#define FL_THUMB (1 << 6) /* Thumb aware */ -#define FL_LDSCHED (1 << 7) /* Load scheduling necessary */ -#define FL_STRONG (1 << 8) /* StrongARM */ -#define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */ -#define FL_XSCALE (1 << 10) /* XScale */ -/* spare (1 << 11) */ -#define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds - media instructions. */ -#define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */ -#define FL_WBUF (1 << 14) /* Schedule for write buffer ops. - Note: ARM6 & 7 derivatives only. */ -#define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */ -#define FL_THUMB2 (1 << 16) /* Thumb-2. */ -#define FL_NOTM (1 << 17) /* Instructions not present in the 'M' - profile. */ -#define FL_THUMB_DIV (1 << 18) /* Hardware divide (Thumb mode). */ -#define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */ -#define FL_NEON (1 << 20) /* Neon instructions. */ -#define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M - architecture. */ -#define FL_ARCH7 (1 << 22) /* Architecture 7. */ -#define FL_ARM_DIV (1 << 23) /* Hardware divide (ARM mode). */ -#define FL_ARCH8 (1 << 24) /* Architecture 8. */ -#define FL_CRC32 (1 << 25) /* ARMv8 CRC32 instructions. */ - -#define FL_SMALLMUL (1 << 26) /* Small multiply supported. */ - -#define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ -#define FL_IWMMXT2 (1 << 30) /* "Intel Wireless MMX2 technology". */ - -/* Flags that only effect tuning, not available instructions. */ -#define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \ - | FL_CO_PROC) - -#define FL_FOR_ARCH2 FL_NOTM -#define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32) -#define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M) -#define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4) -#define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB) -#define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5) -#define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB) -#define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E) -#define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB) -#define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE -#define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6) -#define FL_FOR_ARCH6J FL_FOR_ARCH6 -#define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K) -#define FL_FOR_ARCH6Z FL_FOR_ARCH6 -#define FL_FOR_ARCH6ZK FL_FOR_ARCH6K -#define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2) -#define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM) -#define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7) -#define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K) -#define FL_FOR_ARCH7VE (FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV) -#define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_THUMB_DIV) -#define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV) -#define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM) -#define FL_FOR_ARCH8A (FL_FOR_ARCH7VE | FL_ARCH8) - /* The bits in this mask specify which instructions we are allowed to generate. */ extern unsigned long insn_flags; diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 297dfe1..22b0f44 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -2388,13 +2388,18 @@ extern const char *arm_rewrite_mcpu (int argc, const char **argv); " :%{march=*:-march=%*}}" \ BIG_LITTLE_SPEC +extern const char *arm_is_target_thumb_only (int argc, const char **argv); +#define MODE_SET_SPEC_FUNCTIONS \ + { "target_mode_check", arm_is_target_thumb_only }, + /* -mcpu=native handling only makes sense with compiler running on an ARM chip. */ #if defined(__arm__) extern const char *host_detect_local_cpu (int argc, const char **argv); # define EXTRA_SPEC_FUNCTIONS \ { "local_cpu_detect", host_detect_local_cpu }, \ - BIG_LITTLE_CPU_SPEC_FUNCTIONS + BIG_LITTLE_CPU_SPEC_FUNCTIONS \ + MODE_SET_SPEC_FUNCTIONS # define MCPU_MTUNE_NATIVE_SPECS \ " %{march=native:%