From patchwork Fri Mar 29 09:59:52 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Terry Guo X-Patchwork-Id: 232348 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id D104E2C00B9 for ; Fri, 29 Mar 2013 21:00:37 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; q=dns; s= default; b=RL/yU1NEQ3q2i8gFau9XFlB3wkrd1AXTCfbG5LCS7P0Bcn2lsU96P YVZ2BmRG5uWiA3VShCd96PIMNcNzTrCctzMqYJxZIsG3CQF/30A4GrtsCEeYKU4/ E4yb/4GqpbdfJvGJFwaTUSiWwsfaCbEJD1QXQMDYA0sUBZoVvNady0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; s= default; bh=8XuO5xJQ40MVCfa7pUyGi7GDZRI=; b=kKckRXouR/s86R4kO2+F HdNKrJOd4khITo+GK0WYTsq3vn3Ax5eQh+z/4qj5+2jk5I1mjYJSeRVOh+IYE8VL 3C4eCsPlwnjkpISXBRojYlMaJW2wCGEm328JCOBLbFSXJ4JAyARmIlFvXMWUE507 d1pYkIigjBrZcpCp9tvo4bQ= Received: (qmail 28733 invoked by alias); 29 Mar 2013 10:00:14 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 28466 invoked by uid 89); 29 Mar 2013 10:00:06 -0000 X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL, BAYES_00, KHOP_RCVD_UNTRUST, RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.1 Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Fri, 29 Mar 2013 10:00:01 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Fri, 29 Mar 2013 09:59:58 +0000 Received: from shawin053 ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 29 Mar 2013 09:59:56 +0000 From: "Terry Guo" To: Subject: [Patch/ARM] Cortex-M4 core pipeline patch to tune LDR/STR pairs Date: Fri, 29 Mar 2013 17:59:52 +0800 Message-ID: <000001ce2c64$2a90af80$7fb20e80$@arm.com> MIME-Version: 1.0 X-MC-Unique: 113032909595821101 X-Virus-Found: No Hello, The attached pipeline patch intends to turn following code generation ldr r5, [r4, #12] adds r2, r2, #16 str r5, [r3, #8] to ldr r5, [r4, #12] str r5, [r3, #8] adds r2, r2, #16 The reason is that the STR can be started from the second cycle of its preceding LDR which takes 2 cycles, as long as the result of LDR isn't used as memory address of STR. Tested with various benchmarks on Cortex-M4 MPS. Except one regression caused by register allocation, the others either show performance improvement or no change. Is it OK to trunk? BR, Terry 2013-03-29 Terry Guo * gcc/config/arm/cortex-m4.md: New bypass to tune LDR/STR pairs. From 19dd8bdc9a03f78690700ded911e0cee66328c01 Mon Sep 17 00:00:00 2001 From: Terry Guo Date: Wed, 27 Mar 2013 17:23:09 +0800 Subject: [PATCH] improve m4 pipeline description --- gcc/config/arm/cortex-m4.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/gcc/config/arm/cortex-m4.md b/gcc/config/arm/cortex-m4.md index 187867b..47b0364 100644 --- a/gcc/config/arm/cortex-m4.md +++ b/gcc/config/arm/cortex-m4.md @@ -84,6 +84,10 @@ (eq_attr "type" "store4")) "cortex_m4_ex*5") +(define_bypass 1 "cortex_m4_load1" + "cortex_m4_store1_1,cortex_m4_store1_2" + "arm_no_early_store_addr_dep") + ;; If the address of load or store depends on the result of the preceding ;; instruction, the latency is increased by one.