From patchwork Thu Nov 29 09:57:20 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greta Yorsh X-Patchwork-Id: 202691 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 4C7A82C0082 for ; Thu, 29 Nov 2012 20:57:55 +1100 (EST) Comment: DKIM? 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Set type attribute as appropriate in define_insn patterns with immediate operands. Update pipeline descriptions to use the new values of type attribute. No regression on qemu arm-none-eabi -mcpu=cortex-a15/cortex-a7. Bootstrap successful on Cortex-A15. No difference in generated assembly when compiling all of preprocessed sources of gcc 4.8 as a test in various configurations: -mcpu=cortex-a15 -march=armv6t2 -marm/-mthumb -O0/-O1/-O2/-O3/-Os. The motivation for this patch is cortex-a7 pipeline description, which will be submitted separately. Ok for trunk? Thanks, Greta ChangeLog gcc/ 2012-11-28 Ramana Radhakrishnan Greta Yorsh * config/arm/arm.md (type): Subdivide "alu" into "alu_reg" and "simple_alu_imm". (core_cycles): Use new names. (arm_addsi3): Set type attribute for patterns involving simple_alu_imm. (addsi3_compare0, addsi3_compare0_scratch): Likewise. (addsi3_compare_op1, addsi3_compare_op2, compare_addsi2_op0): Likewise. (compare_addsi2_op1, arm_subsi3_insn, subsi3_compare0): Likewise. (subsi3_compare, arm_decscc,arm_andsi3_insn): Likewise. (thumb1_andsi3_insn, andsi3_compare0_scratch): Likewise. (zeroextractsi_compare0_scratch, iorsi3_insn, iorsi3_compare0): Likewise. (iorsi3_compare0_scratch, arm_xorsi3, thumb1_xorsi3_insn): Likewise. (xorsi3_compare0, xorsi3_compare0_scratch, thumb1_zero_extendhisi2): Likewise. (arm_zero_extendhisi2_v6, thumb1_zero_extendqisi2_v): Likewise. (arm_zero_extendqisi2_v6, thumb1_extendhisi2, arm_extendqisi_v6): Likewise. (thumb1_extendqisi2, arm_movsi_insn): Likewise. (movsi_compare0, movhi_insn_arch4, movhi_bytes): Likewise. (arm_movqi_insn, thumb1_movqi_insn, arm_cmpsi_insn): Likewise. (movsicc_insn, if_plus_move, if_move_plus): Likewise. * config/arm/neon.md (neon_mov/VDX): Likewise. (neon_mov/VQXMOV): Likewise. * config/arm/arm1020e.md (1020alu_op): Likewise. * config/arm/fmp626.md (mp626_alu_op): Likewise. * config/arm/fa726te.md (726te_alu_op): Likewise. * config/arm/fa626te.md (626te_alu_op): Likewise. * config/arm/fa606te.md (606te_alu_op): Likewise. * config/arm/fa526.md (526_alu_op): Likewise. * config/arm/cortex-r4.md (cortex_r4_alu, cortex_r4_mov): Likewise. * config/arm/cortex-m4.md (cortex_m4_alu): Likewise. * config/arm/cortex-a9.md (cprtex_a9_dp): Likewise. * config/arm/cortex-a8.md (cortex_a8_alu, cortex_a8_mov): Likewise. * config/arm/cortex-a5.md (cortex_a5_alu): Likewise. * config/arm/cortex-a15.md (cortex_a15_alu): Likewise. * config/arm/arm926ejs.md (9_alu_op): Likewise. * config/arm/arm1136jfs.md (11_alu_op): Likewise. * config/arm/arm1026ejs.md (alu_op): Likewise. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 7e92b69ad861fe90ed409494d451854f30888462..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -323,8 +323,14 @@ (define_attr "insn" ; Classification of each insn ; Note: vfp.md has different meanings for some of these, and some further ; types as well. See that file for details. -; alu any alu instruction that doesn't hit memory or fp -; regs or have a shifted source operand +; simple_alu_imm a simple alu instruction that doesn't hit memory or fp +; regs or have a shifted source operand and has an immediate +; operand. This currently only tracks very basic immediate +; alu operations. +; alu_reg any alu instruction that doesn't hit memory or fp +; regs or have a shifted source operand +; and does not have an immediate operand. This is +; also the default ; alu_shift any data instruction that doesn't hit memory or fp ; regs, but has a source operand shifted by a constant ; alu_shift_reg any data instruction that doesn't hit memory or fp @@ -354,7 +360,8 @@ (define_attr "insn" ; (define_attr "type" - "alu,\ + "simple_alu_imm,\ + alu_reg,\ alu_shift,\ alu_shift_reg,\ mult,\ @@ -398,7 +405,7 @@ (define_attr "type" (eq_attr "insn" "smulxy,smlaxy,smlalxy,smulwy,smlawx,mul,muls,mla,mlas,\ umull,umulls,umlal,umlals,smull,smulls,smlal,smlals") (const_string "mult") - (const_string "alu"))) + (const_string "alu_reg"))) ; Is this an (integer side) multiply with a 64-bit result? (define_attr "mul64" "no,yes" @@ -536,7 +543,7 @@ (define_attr "write_conflict" "no,yes" ; than one on the main cpu execution unit. (define_attr "core_cycles" "single,multi" (if_then_else (eq_attr "type" - "alu,alu_shift,float,fdivd,fdivs") + "simple_alu_imm,alu_reg,alu_shift,float,fdivd,fdivs") (const_string "single") (const_string "multi"))) @@ -796,7 +803,11 @@ (define_insn_and_split "*arm_addsi3" " [(set_attr "length" "2,4,4,4,4,4,4,4,4,4,4,16") (set_attr "predicable" "yes") - (set_attr "arch" "t2,*,*,*,t2,t2,*,*,a,t2,t2,*")] + (set_attr "arch" "t2,*,*,*,t2,t2,*,*,a,t2,t2,*") + (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") + (const_string "simple_alu_imm") + (const_string "alu_reg"))) + ] ) (define_insn_and_split "*thumb1_addsi3" @@ -865,30 +876,35 @@ (define_peephole2 (define_insn "addsi3_compare0" [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV - (plus:SI (match_operand:SI 1 "s_register_operand" "r, r") - (match_operand:SI 2 "arm_add_operand" "rI,L")) + (plus:SI (match_operand:SI 1 "s_register_operand" "r, r,r") + (match_operand:SI 2 "arm_add_operand" "I,L,r")) (const_int 0))) - (set (match_operand:SI 0 "s_register_operand" "=r,r") + (set (match_operand:SI 0 "s_register_operand" "=r,r,r") (plus:SI (match_dup 1) (match_dup 2)))] "TARGET_ARM" "@ add%.\\t%0, %1, %2 - sub%.\\t%0, %1, #%n2" - [(set_attr "conds" "set")] + sub%.\\t%0, %1, #%n2 + add%.\\t%0, %1, %2" + [(set_attr "conds" "set") + (set_attr "type" "simple_alu_imm, simple_alu_imm, *")] ) (define_insn "*addsi3_compare0_scratch" [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV - (plus:SI (match_operand:SI 0 "s_register_operand" "r, r") - (match_operand:SI 1 "arm_add_operand" "rI,L")) + (plus:SI (match_operand:SI 0 "s_register_operand" "r, r, r") + (match_operand:SI 1 "arm_add_operand" "I,L, r")) (const_int 0)))] "TARGET_ARM" "@ cmn%?\\t%0, %1 - cmp%?\\t%0, #%n1" + cmp%?\\t%0, #%n1 + cmn%?\\t%0, %1" [(set_attr "conds" "set") - (set_attr "predicable" "yes")] + (set_attr "predicable" "yes") + (set_attr "type" "simple_alu_imm, simple_alu_imm, *") + ] ) (define_insn "*compare_negsi_si" @@ -963,59 +979,67 @@ (define_peephole2 (define_insn "*addsi3_compare_op1" [(set (reg:CC_C CC_REGNUM) (compare:CC_C - (plus:SI (match_operand:SI 1 "s_register_operand" "r,r") - (match_operand:SI 2 "arm_add_operand" "rI,L")) + (plus:SI (match_operand:SI 1 "s_register_operand" "r,r,r") + (match_operand:SI 2 "arm_add_operand" "I,L,r")) (match_dup 1))) - (set (match_operand:SI 0 "s_register_operand" "=r,r") + (set (match_operand:SI 0 "s_register_operand" "=r,r,r") (plus:SI (match_dup 1) (match_dup 2)))] "TARGET_32BIT" "@ add%.\\t%0, %1, %2 - sub%.\\t%0, %1, #%n2" - [(set_attr "conds" "set")] + sub%.\\t%0, %1, #%n2 + add%.\\t%0, %1, %2" + [(set_attr "conds" "set") + (set_attr "type" "simple_alu_imm,simple_alu_imm,*")] ) (define_insn "*addsi3_compare_op2" [(set (reg:CC_C CC_REGNUM) (compare:CC_C - (plus:SI (match_operand:SI 1 "s_register_operand" "r,r") - (match_operand:SI 2 "arm_add_operand" "rI,L")) + (plus:SI (match_operand:SI 1 "s_register_operand" "r,r,r") + (match_operand:SI 2 "arm_add_operand" "I,L,r")) (match_dup 2))) - (set (match_operand:SI 0 "s_register_operand" "=r,r") + (set (match_operand:SI 0 "s_register_operand" "=r,r,r") (plus:SI (match_dup 1) (match_dup 2)))] "TARGET_32BIT" "@ add%.\\t%0, %1, %2 + add%.\\t%0, %1, %2 sub%.\\t%0, %1, #%n2" - [(set_attr "conds" "set")] + [(set_attr "conds" "set") + (set_attr "type" "simple_alu_imm,simple_alu_imm,*")] ) (define_insn "*compare_addsi2_op0" [(set (reg:CC_C CC_REGNUM) (compare:CC_C - (plus:SI (match_operand:SI 0 "s_register_operand" "r,r") - (match_operand:SI 1 "arm_add_operand" "rI,L")) + (plus:SI (match_operand:SI 0 "s_register_operand" "r,r,r") + (match_operand:SI 1 "arm_add_operand" "I,L,r")) (match_dup 0)))] "TARGET_32BIT" "@ cmn%?\\t%0, %1 - cmp%?\\t%0, #%n1" + cmp%?\\t%0, #%n1 + cmn%?\\t%0, %1" [(set_attr "conds" "set") - (set_attr "predicable" "yes")] + (set_attr "predicable" "yes") + (set_attr "type" "simple_alu_imm,simple_alu_imm,*")] ) (define_insn "*compare_addsi2_op1" [(set (reg:CC_C CC_REGNUM) (compare:CC_C - (plus:SI (match_operand:SI 0 "s_register_operand" "r,r") - (match_operand:SI 1 "arm_add_operand" "rI,L")) + (plus:SI (match_operand:SI 0 "s_register_operand" "r,r,r") + (match_operand:SI 1 "arm_add_operand" "I,L,r")) (match_dup 1)))] "TARGET_32BIT" "@ cmn%?\\t%0, %1 - cmp%?\\t%0, #%n1" + cmp%?\\t%0, #%n1 + cmn%?\\t%0, %1" [(set_attr "conds" "set") - (set_attr "predicable" "yes")] + (set_attr "predicable" "yes") + (set_attr "type" "simple_alu_imm,simple_alu_imm,*")] ) (define_insn "*addsi3_carryin_" @@ -1253,14 +1277,15 @@ (define_insn "thumb1_subsi3_insn" ; ??? Check Thumb-2 split length (define_insn_and_split "*arm_subsi3_insn" - [(set (match_operand:SI 0 "s_register_operand" "=r,r,rk,r") - (minus:SI (match_operand:SI 1 "reg_or_int_operand" "rI,r,k,?n") - (match_operand:SI 2 "reg_or_int_operand" "r,rI,r, r")))] + [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,rk,r") + (minus:SI (match_operand:SI 1 "reg_or_int_operand" "rI,r,r,k,?n") + (match_operand:SI 2 "reg_or_int_operand" "r,I,r,r, r")))] "TARGET_32BIT" "@ rsb%?\\t%0, %2, %1 sub%?\\t%0, %1, %2 sub%?\\t%0, %1, %2 + sub%?\\t%0, %1, %2 #" "&& (CONST_INT_P (operands[1]) && !const_ok_for_arm (INTVAL (operands[1])))" @@ -1270,8 +1295,9 @@ (define_insn_and_split "*arm_subsi3_insn INTVAL (operands[1]), operands[0], operands[2], 0); DONE; " - [(set_attr "length" "4,4,4,16") - (set_attr "predicable" "yes")] + [(set_attr "length" "4,4,4,4,16") + (set_attr "predicable" "yes") + (set_attr "type" "*,simple_alu_imm,*,*,*")] ) (define_peephole2 @@ -1290,29 +1316,33 @@ (define_peephole2 (define_insn "*subsi3_compare0" [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV - (minus:SI (match_operand:SI 1 "arm_rhs_operand" "r,I") - (match_operand:SI 2 "arm_rhs_operand" "rI,r")) + (minus:SI (match_operand:SI 1 "arm_rhs_operand" "r,r,I") + (match_operand:SI 2 "arm_rhs_operand" "I,r,r")) (const_int 0))) - (set (match_operand:SI 0 "s_register_operand" "=r,r") + (set (match_operand:SI 0 "s_register_operand" "=r,r,r") (minus:SI (match_dup 1) (match_dup 2)))] "TARGET_32BIT" "@ sub%.\\t%0, %1, %2 + sub%.\\t%0, %1, %2 rsb%.\\t%0, %2, %1" - [(set_attr "conds" "set")] + [(set_attr "conds" "set") + (set_attr "type" "simple_alu_imm,*,*")] ) (define_insn "*subsi3_compare" [(set (reg:CC CC_REGNUM) - (compare:CC (match_operand:SI 1 "arm_rhs_operand" "r,I") - (match_operand:SI 2 "arm_rhs_operand" "rI,r"))) - (set (match_operand:SI 0 "s_register_operand" "=r,r") + (compare:CC (match_operand:SI 1 "arm_rhs_operand" "r,r,I") + (match_operand:SI 2 "arm_rhs_operand" "I,r,r"))) + (set (match_operand:SI 0 "s_register_operand" "=r,r,r") (minus:SI (match_dup 1) (match_dup 2)))] "TARGET_32BIT" "@ sub%.\\t%0, %1, %2 + sub%.\\t%0, %1, %2 rsb%.\\t%0, %2, %1" - [(set_attr "conds" "set")] + [(set_attr "conds" "set") + (set_attr "type" "simple_alu_imm,*,*")] ) (define_expand "decscc" @@ -1334,7 +1364,8 @@ (define_insn "*arm_decscc" sub%d2\\t%0, %1, #1 mov%D2\\t%0, %1\;sub%d2\\t%0, %1, #1" [(set_attr "conds" "use") - (set_attr "length" "*,8")] + (set_attr "length" "*,8") + (set_attr "type" "simple_alu_imm,*")] ) (define_expand "subsf3" @@ -2190,13 +2221,14 @@ (define_expand "andsi3" ; ??? Check split length for Thumb-2 (define_insn_and_split "*arm_andsi3_insn" - [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") - (and:SI (match_operand:SI 1 "s_register_operand" "r,r,r") - (match_operand:SI 2 "reg_or_int_operand" "rI,K,?n")))] + [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r") + (and:SI (match_operand:SI 1 "s_register_operand" "r,r,r,r") + (match_operand:SI 2 "reg_or_int_operand" "I,K,r,?n")))] "TARGET_32BIT" "@ and%?\\t%0, %1, %2 bic%?\\t%0, %1, #%B2 + and%?\\t%0, %1, %2 #" "TARGET_32BIT && CONST_INT_P (operands[2]) @@ -2208,8 +2240,9 @@ (define_insn_and_split "*arm_andsi3_insn INTVAL (operands[2]), operands[0], operands[1], 0); DONE; " - [(set_attr "length" "4,4,16") - (set_attr "predicable" "yes")] + [(set_attr "length" "4,4,4,16") + (set_attr "predicable" "yes") + (set_attr "type" "simple_alu_imm,simple_alu_imm,*,simple_alu_imm")] ) (define_insn "*thumb1_andsi3_insn" @@ -2219,35 +2252,40 @@ (define_insn "*thumb1_andsi3_insn" "TARGET_THUMB1" "and\\t%0, %2" [(set_attr "length" "2") + (set_attr "type" "simple_alu_imm") (set_attr "conds" "set")]) (define_insn "*andsi3_compare0" [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV - (and:SI (match_operand:SI 1 "s_register_operand" "r,r") - (match_operand:SI 2 "arm_not_operand" "rI,K")) + (and:SI (match_operand:SI 1 "s_register_operand" "r,r,r") + (match_operand:SI 2 "arm_not_operand" "I,K,r")) (const_int 0))) - (set (match_operand:SI 0 "s_register_operand" "=r,r") + (set (match_operand:SI 0 "s_register_operand" "=r,r,r") (and:SI (match_dup 1) (match_dup 2)))] "TARGET_32BIT" "@ and%.\\t%0, %1, %2 - bic%.\\t%0, %1, #%B2" - [(set_attr "conds" "set")] + bic%.\\t%0, %1, #%B2 + and%.\\t%0, %1, %2" + [(set_attr "conds" "set") + (set_attr "type" "simple_alu_imm,simple_alu_imm,*")] ) (define_insn "*andsi3_compare0_scratch" [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV - (and:SI (match_operand:SI 0 "s_register_operand" "r,r") - (match_operand:SI 1 "arm_not_operand" "rI,K")) + (and:SI (match_operand:SI 0 "s_register_operand" "r,r,r") + (match_operand:SI 1 "arm_not_operand" "I,K,r")) (const_int 0))) - (clobber (match_scratch:SI 2 "=X,r"))] + (clobber (match_scratch:SI 2 "=X,r,X"))] "TARGET_32BIT" "@ tst%?\\t%0, %1 - bic%.\\t%2, %0, #%B1" - [(set_attr "conds" "set")] + bic%.\\t%2, %0, #%B1 + tst%?\\t%0, %1" + [(set_attr "conds" "set") + (set_attr "type" "simple_alu_imm,simple_alu_imm,*")] ) (define_insn "*zeroextractsi_compare0_scratch" @@ -2269,7 +2307,8 @@ (define_insn "*zeroextractsi_compare0_sc return \"\"; " [(set_attr "conds" "set") - (set_attr "predicable" "yes")] + (set_attr "predicable" "yes") + (set_attr "type" "simple_alu_imm")] ) (define_insn_and_split "*ne_zeroextractsi" @@ -2916,13 +2955,14 @@ (define_expand "iorsi3" ) (define_insn_and_split "*iorsi3_insn" - [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") - (ior:SI (match_operand:SI 1 "s_register_operand" "%r,r,r") - (match_operand:SI 2 "reg_or_int_operand" "rI,K,?n")))] + [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r") + (ior:SI (match_operand:SI 1 "s_register_operand" "%r,r,r,r") + (match_operand:SI 2 "reg_or_int_operand" "I,K,r,?n")))] "TARGET_32BIT" "@ orr%?\\t%0, %1, %2 orn%?\\t%0, %1, #%B2 + orr%?\\t%0, %1, %2 #" "TARGET_32BIT && CONST_INT_P (operands[2]) @@ -2934,9 +2974,11 @@ (define_insn_and_split "*iorsi3_insn" INTVAL (operands[2]), operands[0], operands[1], 0); DONE; } - [(set_attr "length" "4,4,16") - (set_attr "arch" "32,t2,32") - (set_attr "predicable" "yes")]) + [(set_attr "length" "4,4,4,16") + (set_attr "arch" "32,t2,32,32") + (set_attr "predicable" "yes") + (set_attr "type" "simple_alu_imm,simple_alu_imm,*,*")] +) (define_insn "*thumb1_iorsi3_insn" [(set (match_operand:SI 0 "register_operand" "=l") @@ -2962,25 +3004,27 @@ (define_peephole2 (define_insn "*iorsi3_compare0" [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r") - (match_operand:SI 2 "arm_rhs_operand" "rI")) + (compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r,r") + (match_operand:SI 2 "arm_rhs_operand" "I,r")) (const_int 0))) - (set (match_operand:SI 0 "s_register_operand" "=r") + (set (match_operand:SI 0 "s_register_operand" "=r,r") (ior:SI (match_dup 1) (match_dup 2)))] "TARGET_32BIT" "orr%.\\t%0, %1, %2" - [(set_attr "conds" "set")] + [(set_attr "conds" "set") + (set_attr "type" "simple_alu_imm,*")] ) (define_insn "*iorsi3_compare0_scratch" [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r") - (match_operand:SI 2 "arm_rhs_operand" "rI")) + (compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r,r") + (match_operand:SI 2 "arm_rhs_operand" "I,r")) (const_int 0))) - (clobber (match_scratch:SI 0 "=r"))] + (clobber (match_scratch:SI 0 "=r,r"))] "TARGET_32BIT" "orr%.\\t%0, %1, %2" - [(set_attr "conds" "set")] + [(set_attr "conds" "set") + (set_attr "type" "simple_alu_imm, *")] ) (define_expand "xordi3" @@ -3054,12 +3098,13 @@ (define_expand "xorsi3" ) (define_insn_and_split "*arm_xorsi3" - [(set (match_operand:SI 0 "s_register_operand" "=r,r") - (xor:SI (match_operand:SI 1 "s_register_operand" "%r,r") - (match_operand:SI 2 "reg_or_int_operand" "rI,?n")))] + [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") + (xor:SI (match_operand:SI 1 "s_register_operand" "%r,r,r") + (match_operand:SI 2 "reg_or_int_operand" "I,r,?n")))] "TARGET_32BIT" "@ eor%?\\t%0, %1, %2 + eor%?\\t%0, %1, %2 #" "TARGET_32BIT && CONST_INT_P (operands[2]) @@ -3070,8 +3115,9 @@ (define_insn_and_split "*arm_xorsi3" INTVAL (operands[2]), operands[0], operands[1], 0); DONE; } - [(set_attr "length" "4,16") - (set_attr "predicable" "yes")] + [(set_attr "length" "4,4,16") + (set_attr "predicable" "yes") + (set_attr "type" "simple_alu_imm,*,*")] ) (define_insn "*thumb1_xorsi3_insn" @@ -3081,28 +3127,32 @@ (define_insn "*thumb1_xorsi3_insn" "TARGET_THUMB1" "eor\\t%0, %2" [(set_attr "length" "2") - (set_attr "conds" "set")]) + (set_attr "conds" "set") + (set_attr "type" "simple_alu_imm")] +) (define_insn "*xorsi3_compare0" [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (xor:SI (match_operand:SI 1 "s_register_operand" "r") - (match_operand:SI 2 "arm_rhs_operand" "rI")) + (compare:CC_NOOV (xor:SI (match_operand:SI 1 "s_register_operand" "r,r") + (match_operand:SI 2 "arm_rhs_operand" "I,r")) (const_int 0))) - (set (match_operand:SI 0 "s_register_operand" "=r") + (set (match_operand:SI 0 "s_register_operand" "=r,r") (xor:SI (match_dup 1) (match_dup 2)))] "TARGET_32BIT" "eor%.\\t%0, %1, %2" - [(set_attr "conds" "set")] + [(set_attr "conds" "set") + (set_attr "type" "simple_alu_imm,*")] ) (define_insn "*xorsi3_compare0_scratch" [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (xor:SI (match_operand:SI 0 "s_register_operand" "r") - (match_operand:SI 1 "arm_rhs_operand" "rI")) + (compare:CC_NOOV (xor:SI (match_operand:SI 0 "s_register_operand" "r,r") + (match_operand:SI 1 "arm_rhs_operand" "I,r")) (const_int 0)))] "TARGET_32BIT" "teq%?\\t%0, %1" - [(set_attr "conds" "set")] + [(set_attr "conds" "set") + (set_attr "type" "simple_alu_imm, *")] ) ; By splitting (IOR (AND (NOT A) (NOT B)) C) as D = AND (IOR A B) (NOT C), @@ -4663,7 +4713,11 @@ (define_insn "*thumb1_zero_extendhisi2" [(if_then_else (eq_attr "is_arch6" "yes") (const_int 2) (const_int 4)) (const_int 4)]) - (set_attr "type" "alu_shift,load_byte")] + (set_attr_alternative "type" + [(if_then_else (eq_attr "tune" "cortexa7") + (const_string "simple_alu_imm") + (const_string "alu_shift")) + (const_string "load_byte")])] ) (define_insn "*arm_zero_extendhisi2" @@ -4684,8 +4738,12 @@ (define_insn "*arm_zero_extendhisi2_v6" "@ uxth%?\\t%0, %1 ldr%(h%)\\t%0, %1" - [(set_attr "type" "alu_shift,load_byte") - (set_attr "predicable" "yes")] + [(set_attr "predicable" "yes") + (set_attr_alternative "type" + [(if_then_else (eq_attr "tune" "cortexa7") + (const_string "simple_alu_imm") + (const_string "alu_shift")) + (const_string "load_byte")])] ) (define_insn "*arm_zero_extendhisi2addsi" @@ -4755,7 +4813,11 @@ (define_insn "*thumb1_zero_extendqisi2_v uxtb\\t%0, %1 ldrb\\t%0, %1" [(set_attr "length" "2") - (set_attr "type" "alu_shift,load_byte")] + (set_attr_alternative "type" + [(if_then_else (eq_attr "tune" "cortexa7") + (const_string "simple_alu_imm") + (const_string "alu_shift")) + (const_string "load_byte")])] ) (define_insn "*arm_zero_extendqisi2" @@ -4777,7 +4839,11 @@ (define_insn "*arm_zero_extendqisi2_v6" "@ uxtb%(%)\\t%0, %1 ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2" - [(set_attr "type" "alu_shift,load_byte") + [(set_attr_alternative "type" + [(if_then_else (eq_attr "tune" "cortexa7") + (const_string "simple_alu_imm") + (const_string "alu_shift")) + (const_string "load_byte")]) (set_attr "predicable" "yes")] ) @@ -4951,7 +5017,11 @@ (define_insn "thumb1_extendhisi2" [(if_then_else (eq_attr "is_arch6" "yes") (const_int 2) (const_int 4)) (const_int 4)]) - (set_attr "type" "alu_shift,load_byte") + (set_attr_alternative "type" + [(if_then_else (eq_attr "tune" "cortexa7") + (const_string "simple_alu_imm") + (const_string "alu_shift")) + (const_string "load_byte")]) (set_attr "pool_range" "*,1020")] ) @@ -5024,7 +5094,11 @@ (define_insn "*arm_extendhisi2_v6" "@ sxth%?\\t%0, %1 ldr%(sh%)\\t%0, %1" - [(set_attr "type" "alu_shift,load_byte") + [(set_attr_alternative "type" + [(if_then_else (eq_attr "tune" "cortexa7") + (const_string "simple_alu_imm") + (const_string "alu_shift")) + (const_string "load_byte")]) (set_attr "predicable" "yes") (set_attr "pool_range" "*,256") (set_attr "neg_pool_range" "*,244")] @@ -5124,7 +5198,11 @@ (define_insn "*arm_extendqisi_v6" "@ sxtb%?\\t%0, %1 ldr%(sb%)\\t%0, %1" - [(set_attr "type" "alu_shift,load_byte") + [(set_attr_alternative "type" + [(if_then_else (eq_attr "tune" "cortexa7") + (const_string "simple_alu_imm") + (const_string "alu_shift")) + (const_string "load_byte")]) (set_attr "predicable" "yes") (set_attr "pool_range" "*,256") (set_attr "neg_pool_range" "*,244")] @@ -5237,7 +5315,12 @@ (define_insn "thumb1_extendqisi2" (const_int 2) (if_then_else (eq_attr "is_arch6" "yes") (const_int 4) (const_int 6))]) - (set_attr "type" "alu_shift,load_byte,load_byte")] + (set_attr_alternative "type" + [(if_then_else (eq_attr "tune" "cortexa7") + (const_string "simple_alu_imm") + (const_string "alu_shift")) + (const_string "load_byte") + (const_string "load_byte")])] ) (define_expand "extendsfdf2" @@ -5611,7 +5694,7 @@ (define_insn "*arm_movsi_insn" movw%?\\t%0, %1 ldr%?\\t%0, %1 str%?\\t%1, %0" - [(set_attr "type" "*,*,*,*,load1,store1") + [(set_attr "type" "*,simple_alu_imm,simple_alu_imm,simple_alu_imm,load1,store1") (set_attr "insn" "mov,mov,mvn,mov,*,*") (set_attr "predicable" "yes") (set_attr "pool_range" "*,*,*,*,4096,*") @@ -5910,7 +5993,8 @@ (define_insn "*movsi_compare0" "@ cmp%?\\t%0, #0 sub%.\\t%0, %1, #0" - [(set_attr "conds" "set")] + [(set_attr "conds" "set") + (set_attr "type" "simple_alu_imm,simple_alu_imm")] ) ;; Subroutine to store a half word from a register into memory. @@ -6323,22 +6407,30 @@ (define_insn "*movhi_insn_arch4" mvn%?\\t%0, #%B1\\t%@ movhi str%(h%)\\t%1, %0\\t%@ movhi ldr%(h%)\\t%0, %1\\t%@ movhi" - [(set_attr "type" "*,*,store1,load1") - (set_attr "predicable" "yes") + [(set_attr "predicable" "yes") (set_attr "insn" "mov,mvn,*,*") (set_attr "pool_range" "*,*,*,256") - (set_attr "neg_pool_range" "*,*,*,244")] + (set_attr "neg_pool_range" "*,*,*,244") + (set_attr_alternative "type" + [(if_then_else (match_operand 1 "const_int_operand" "") + (const_string "simple_alu_imm" ) + (const_string "*")) + (const_string "simple_alu_imm") + (const_string "store1") + (const_string "load1")])] ) (define_insn "*movhi_bytes" - [(set (match_operand:HI 0 "s_register_operand" "=r,r") - (match_operand:HI 1 "arm_rhs_operand" "rI,K"))] + [(set (match_operand:HI 0 "s_register_operand" "=r,r,r") + (match_operand:HI 1 "arm_rhs_operand" "I,r,K"))] "TARGET_ARM" "@ mov%?\\t%0, %1\\t%@ movhi + mov%?\\t%0, %1\\t%@ movhi mvn%?\\t%0, #%B1\\t%@ movhi" [(set_attr "predicable" "yes") - (set_attr "insn" "mov,mvn")] + (set_attr "insn" "mov, mov,mvn") + (set_attr "type" "simple_alu_imm,*,simple_alu_imm")] ) (define_expand "thumb_movhi_clobber" @@ -6463,23 +6555,24 @@ (define_expand "movqi" (define_insn "*arm_movqi_insn" - [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,l,Uu,r,m") - (match_operand:QI 1 "general_operand" "rI,K,Uu,l,m,r"))] + [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,l,Uu,r,m") + (match_operand:QI 1 "general_operand" "r,I,K,Uu,l,m,r"))] "TARGET_32BIT && ( register_operand (operands[0], QImode) || register_operand (operands[1], QImode))" "@ mov%?\\t%0, %1 + mov%?\\t%0, %1 mvn%?\\t%0, #%B1 ldr%(b%)\\t%0, %1 str%(b%)\\t%1, %0 ldr%(b%)\\t%0, %1 str%(b%)\\t%1, %0" - [(set_attr "type" "*,*,load1,store1,load1,store1") - (set_attr "insn" "mov,mvn,*,*,*,*") + [(set_attr "type" "*,simple_alu_imm,simple_alu_imm,load1, store1, load1, store1") + (set_attr "insn" "mov,mov,mvn,*,*,*,*") (set_attr "predicable" "yes") - (set_attr "arch" "any,any,t2,t2,any,any") - (set_attr "length" "4,4,2,2,4,4")] + (set_attr "arch" "any,any,any,t2,t2,any,any") + (set_attr "length" "4,4,4,2,2,4,4")] ) (define_insn "*thumb1_movqi_insn" @@ -6496,7 +6589,7 @@ (define_insn "*thumb1_movqi_insn" mov\\t%0, %1 mov\\t%0, %1" [(set_attr "length" "2") - (set_attr "type" "*,load1,store1,*,*,*") + (set_attr "type" "simple_alu_imm,load1,store1,*,*,simple_alu_imm") (set_attr "insn" "*,*,*,mov,mov,mov") (set_attr "pool_range" "*,32,*,*,*,*") (set_attr "conds" "clob,nocond,nocond,nocond,nocond,clob")]) @@ -7617,7 +7710,8 @@ (define_insn "*arm_cmpsi_insn" [(set_attr "conds" "set") (set_attr "arch" "t2,t2,any,any") (set_attr "length" "2,2,4,4") - (set_attr "predicable" "yes")] + (set_attr "predicable" "yes") + (set_attr "type" "*,*,*,simple_alu_imm")] ) (define_insn "*cmpsi_shiftsi" @@ -8182,7 +8276,20 @@ (define_insn "*movsicc_insn" mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2" [(set_attr "length" "4,4,4,4,8,8,8,8") (set_attr "conds" "use") - (set_attr "insn" "mov,mvn,mov,mvn,mov,mov,mvn,mvn")] + (set_attr "insn" "mov,mvn,mov,mvn,mov,mov,mvn,mvn") + (set_attr_alternative "type" + [(if_then_else (match_operand 2 "const_int_operand" "") + (const_string "simple_alu_imm") + (const_string "*")) + (const_string "simple_alu_imm") + (if_then_else (match_operand 1 "const_int_operand" "") + (const_string "simple_alu_imm") + (const_string "*")) + (const_string "simple_alu_imm") + (const_string "*") + (const_string "*") + (const_string "*") + (const_string "*")])] ) (define_insn "*movsfcc_soft_insn" @@ -9982,7 +10089,13 @@ (define_insn "*if_plus_move" sub%d4\\t%0, %2, #%n3\;mov%D4\\t%0, %1" [(set_attr "conds" "use") (set_attr "length" "4,4,8,8") - (set_attr "type" "*,*,*,*")] + (set_attr_alternative "type" + [(if_then_else (match_operand 3 "const_int_operand" "") + (const_string "simple_alu_imm" ) + (const_string "*")) + (const_string "simple_alu_imm") + (const_string "*") + (const_string "*")])] ) (define_insn "*ifcompare_move_plus" @@ -10018,7 +10131,13 @@ (define_insn "*if_move_plus" sub%D4\\t%0, %2, #%n3\;mov%d4\\t%0, %1" [(set_attr "conds" "use") (set_attr "length" "4,4,8,8") - (set_attr "type" "*,*,*,*")] + (set_attr_alternative "type" + [(if_then_else (match_operand 3 "const_int_operand" "") + (const_string "simple_alu_imm" ) + (const_string "*")) + (const_string "simple_alu_imm") + (const_string "*") + (const_string "*")])] ) (define_insn "*ifcompare_arith_arith" diff --git a/gcc/config/arm/arm1020e.md b/gcc/config/arm/arm1020e.md index 280af12f93222ce76ab0351898d567e3017fc34e..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/arm1020e.md +++ b/gcc/config/arm/arm1020e.md @@ -66,7 +66,7 @@ (define_cpu_unit "1020l_e,1020l_m,1020l_ ;; ALU operations with no shifted operand (define_insn_reservation "1020alu_op" 1 (and (eq_attr "tune" "arm1020e,arm1022e") - (eq_attr "type" "alu")) + (eq_attr "type" "alu_reg,simple_alu_imm")) "1020a_e,1020a_m,1020a_w") ;; ALU operations with a shift-by-constant operand diff --git a/gcc/config/arm/arm1026ejs.md b/gcc/config/arm/arm1026ejs.md index e6221363898102c566f8be5423f5509a0df49acd..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/arm1026ejs.md +++ b/gcc/config/arm/arm1026ejs.md @@ -66,7 +66,7 @@ (define_cpu_unit "l_e,l_m,l_w" "arm1026e ;; ALU operations with no shifted operand (define_insn_reservation "alu_op" 1 (and (eq_attr "tune" "arm1026ejs") - (eq_attr "type" "alu")) + (eq_attr "type" "alu_reg,simple_alu_imm")) "a_e,a_m,a_w") ;; ALU operations with a shift-by-constant operand diff --git a/gcc/config/arm/arm1136jfs.md b/gcc/config/arm/arm1136jfs.md index 8fc30e976f0fbfe45f360ee93706cf64f9ef8f08..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/arm1136jfs.md +++ b/gcc/config/arm/arm1136jfs.md @@ -75,7 +75,7 @@ (define_cpu_unit "l_a,l_dc1,l_dc2,l_wb" ;; ALU operations with no shifted operand (define_insn_reservation "11_alu_op" 2 (and (eq_attr "tune" "arm1136js,arm1136jfs") - (eq_attr "type" "alu")) + (eq_attr "type" "alu_reg,simple_alu_imm")) "e_1,e_2,e_3,e_wb") ;; ALU operations with a shift-by-constant operand diff --git a/gcc/config/arm/arm926ejs.md b/gcc/config/arm/arm926ejs.md index d3908f9e3ecd972c6f93a77bfd1bde4e501dcdba..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/arm926ejs.md +++ b/gcc/config/arm/arm926ejs.md @@ -58,7 +58,7 @@ (define_cpu_unit "e,m,w" "arm926ejs") ;; ALU operations with no shifted operand (define_insn_reservation "9_alu_op" 1 (and (eq_attr "tune" "arm926ejs") - (eq_attr "type" "alu,alu_shift")) + (eq_attr "type" "alu_reg,simple_alu_imm,alu_shift")) "e,m,w") ;; ALU operations with a shift-by-register operand diff --git a/gcc/config/arm/cortex-a15.md b/gcc/config/arm/cortex-a15.md index b86c6e706900b81adea9c5a487b96bcb473b8f62..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/cortex-a15.md +++ b/gcc/config/arm/cortex-a15.md @@ -61,7 +61,7 @@ (define_cpu_unit "ca15_sx2_alu, ca15_sx2 ;; Simple ALU without shift (define_insn_reservation "cortex_a15_alu" 2 (and (eq_attr "tune" "cortexa15") - (and (eq_attr "type" "alu") + (and (eq_attr "type" "alu_reg,simple_alu_imm") (eq_attr "neon_type" "none"))) "ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)") diff --git a/gcc/config/arm/cortex-a5.md b/gcc/config/arm/cortex-a5.md index eb154e2980382befc77027ec8a0a35fcc34a1ff5..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/cortex-a5.md +++ b/gcc/config/arm/cortex-a5.md @@ -58,7 +58,7 @@ (define_cpu_unit "cortex_a5_fp_div_sqrt" (define_insn_reservation "cortex_a5_alu" 2 (and (eq_attr "tune" "cortexa5") - (eq_attr "type" "alu")) + (eq_attr "type" "alu_reg,simple_alu_imm")) "cortex_a5_ex1") (define_insn_reservation "cortex_a5_alu_shift" 2 diff --git a/gcc/config/arm/cortex-a8.md b/gcc/config/arm/cortex-a8.md index 1922e5cf4c66c147830ba3e7b195263a3aac3015..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/cortex-a8.md +++ b/gcc/config/arm/cortex-a8.md @@ -85,7 +85,7 @@ (define_reservation "cortex_a8_multiply_ ;; (source read in E2 and destination available at the end of that cycle). (define_insn_reservation "cortex_a8_alu" 2 (and (eq_attr "tune" "cortexa8") - (ior (and (and (eq_attr "type" "alu") + (ior (and (and (eq_attr "type" "alu_reg,simple_alu_imm") (eq_attr "neon_type" "none")) (not (eq_attr "insn" "mov,mvn"))) (eq_attr "insn" "clz"))) @@ -107,7 +107,7 @@ (define_insn_reservation "cortex_a8_alu_ (define_insn_reservation "cortex_a8_mov" 1 (and (eq_attr "tune" "cortexa8") - (and (eq_attr "type" "alu,alu_shift,alu_shift_reg") + (and (eq_attr "type" "alu_reg,simple_alu_imm,alu_shift,alu_shift_reg") (eq_attr "insn" "mov,mvn"))) "cortex_a8_default") diff --git a/gcc/config/arm/cortex-a9.md b/gcc/config/arm/cortex-a9.md index 12c19efb12132e932dea03031ed5fd364e4b9aef..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/cortex-a9.md +++ b/gcc/config/arm/cortex-a9.md @@ -80,7 +80,7 @@ (define_reservation "cortex_a9_mult_long ;; which can go down E2 without any problem. (define_insn_reservation "cortex_a9_dp" 2 (and (eq_attr "tune" "cortexa9") - (ior (and (eq_attr "type" "alu") + (ior (and (eq_attr "type" "alu_reg,simple_alu_imm") (eq_attr "neon_type" "none")) (and (and (eq_attr "type" "alu_shift_reg, alu_shift") (eq_attr "insn" "mov")) diff --git a/gcc/config/arm/cortex-m4.md b/gcc/config/arm/cortex-m4.md index 57479853610ebdcdff8db4cc5ff3052c1a09b276..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/cortex-m4.md +++ b/gcc/config/arm/cortex-m4.md @@ -31,7 +31,7 @@ (define_reservation "cortex_m4_ex" "cort ;; ALU and multiply is one cycle. (define_insn_reservation "cortex_m4_alu" 1 (and (eq_attr "tune" "cortexm4") - (eq_attr "type" "alu,alu_shift,alu_shift_reg,mult")) + (eq_attr "type" "alu_reg,simple_alu_imm,alu_shift,alu_shift_reg,mult")) "cortex_m4_ex") ;; Byte, half-word and word load is two cycles. diff --git a/gcc/config/arm/cortex-r4.md b/gcc/config/arm/cortex-r4.md index e26c3d45d5e6c5926500510c653619fb2a686851..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/cortex-r4.md +++ b/gcc/config/arm/cortex-r4.md @@ -78,13 +78,13 @@ (define_reservation "cortex_r4_branch" " ;; for the purposes of the dual-issue constraints above. (define_insn_reservation "cortex_r4_alu" 2 (and (eq_attr "tune_cortexr4" "yes") - (and (eq_attr "type" "alu") + (and (eq_attr "type" "alu_reg,simple_alu_imm") (not (eq_attr "insn" "mov")))) "cortex_r4_alu") (define_insn_reservation "cortex_r4_mov" 2 (and (eq_attr "tune_cortexr4" "yes") - (and (eq_attr "type" "alu") + (and (eq_attr "type" "alu_reg,simple_alu_imm") (eq_attr "insn" "mov"))) "cortex_r4_mov") diff --git a/gcc/config/arm/fa526.md b/gcc/config/arm/fa526.md index 42eb9b272fb1b9df553c566e8c41cb4d44c306ca..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/fa526.md +++ b/gcc/config/arm/fa526.md @@ -62,7 +62,7 @@ (define_cpu_unit "fa526_core" "fa526") ;; ALU operations (define_insn_reservation "526_alu_op" 1 (and (eq_attr "tune" "fa526") - (eq_attr "type" "alu")) + (eq_attr "type" "alu_reg,simple_alu_imm")) "fa526_core") (define_insn_reservation "526_alu_shift_op" 2 diff --git a/gcc/config/arm/fa606te.md b/gcc/config/arm/fa606te.md index 06e63d696bde2e13556982e053cf2b0fd719d1ce..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/fa606te.md +++ b/gcc/config/arm/fa606te.md @@ -62,7 +62,7 @@ (define_cpu_unit "fa606te_core" "fa606te ;; ALU operations (define_insn_reservation "606te_alu_op" 1 (and (eq_attr "tune" "fa606te") - (eq_attr "type" "alu,alu_shift,alu_shift_reg")) + (eq_attr "type" "alu_reg,simple_alu_imm,alu_shift,alu_shift_reg")) "fa606te_core") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; diff --git a/gcc/config/arm/fa626te.md b/gcc/config/arm/fa626te.md index 7fe1c8724bef3feae8a291777379a5dac3cf31d1..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/fa626te.md +++ b/gcc/config/arm/fa626te.md @@ -68,7 +68,7 @@ (define_cpu_unit "fa626te_core" "fa626te ;; ALU operations (define_insn_reservation "626te_alu_op" 1 (and (eq_attr "tune" "fa626,fa626te") - (eq_attr "type" "alu")) + (eq_attr "type" "alu_reg,simple_alu_imm")) "fa626te_core") (define_insn_reservation "626te_alu_shift_op" 2 diff --git a/gcc/config/arm/fa726te.md b/gcc/config/arm/fa726te.md index 3c33d59710478a5a46435e4df3177bbfcca1faff..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/fa726te.md +++ b/gcc/config/arm/fa726te.md @@ -85,7 +85,7 @@ (define_insn_reservation "726te_shift_op ;; Other ALU instructions 2 cycles. (define_insn_reservation "726te_alu_op" 1 (and (eq_attr "tune" "fa726te") - (and (eq_attr "type" "alu") + (and (eq_attr "type" "alu_reg,simple_alu_imm") (not (eq_attr "insn" "mov,mvn")))) "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)") diff --git a/gcc/config/arm/fmp626.md b/gcc/config/arm/fmp626.md index 9ba33ddec4741ef3124c23ca8cf9f42f38feb6c8..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/fmp626.md +++ b/gcc/config/arm/fmp626.md @@ -63,7 +63,7 @@ (define_cpu_unit "fmp626_core" "fmp626") ;; ALU operations (define_insn_reservation "mp626_alu_op" 1 (and (eq_attr "tune" "fmp626") - (eq_attr "type" "alu")) + (eq_attr "type" "alu_reg,simple_alu_imm")) "fmp626_core") (define_insn_reservation "mp626_alu_shift_op" 2 diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 21035808c0e5964d29b7c903b5721210223153e0..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -193,7 +193,7 @@ (define_insn "*neon_mov" } } [(set_attr "neon_type" "neon_int_1,*,neon_vmov,*,neon_mrrc,neon_mcr_2_mcrr,*,*,*") - (set_attr "type" "*,f_stored,*,f_loadd,*,*,alu,load2,store2") + (set_attr "type" "*,f_stored,*,f_loadd,*,*,alu_reg,load2,store2") (set_attr "insn" "*,*,*,*,*,*,mov,*,*") (set_attr "length" "4,4,4,4,4,4,8,8,8") (set_attr "pool_range" "*,*,*,1020,*,*,*,1020,*") @@ -238,7 +238,7 @@ (define_insn "*neon_mov" } [(set_attr "neon_type" "neon_int_1,neon_stm_2,neon_vmov,neon_ldm_2,\ neon_mrrc,neon_mcr_2_mcrr,*,*,*") - (set_attr "type" "*,*,*,*,*,*,alu,load4,store4") + (set_attr "type" "*,*,*,*,*,*,alu_reg,load4,store4") (set_attr "insn" "*,*,*,*,*,*,mov,*,*") (set_attr "length" "4,8,4,8,8,8,16,8,16") (set_attr "pool_range" "*,*,*,1020,*,*,*,1020,*") diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index a5302f479f5091d08f4bf1a9ee9b0423692372af..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -1,5 +1,5 @@ ;; ARM Thumb-2 Machine Description -;; Copyright (C) 2007, 2008, 2010 Free Software Foundation, Inc. +;; Copyright (C) 2007, 2008, 2010, 2012 Free Software Foundation, Inc. ;; Written by CodeSourcery, LLC. ;; ;; This file is part of GCC. @@ -180,7 +180,7 @@ (define_insn "*thumb2_movsi_insn" ldr%?\\t%0, %1 str%?\\t%1, %0 str%?\\t%1, %0" - [(set_attr "type" "*,*,*,*,load1,load1,store1,store1") + [(set_attr "type" "*,*,simple_alu_imm,*,load1,load1,store1,store1") (set_attr "predicable" "yes") (set_attr "pool_range" "*,*,*,*,1020,4096,*,*") (set_attr "neg_pool_range" "*,*,*,*,0,0,*,*")] @@ -568,7 +568,11 @@ (define_insn "*thumb2_extendqisi_v6" "@ sxtb%?\\t%0, %1 ldr%(sb%)\\t%0, %1" - [(set_attr "type" "alu_shift,load_byte") + [(set_attr_alternative "type" + [(if_then_else (eq_attr "tune" "cortexa7") + (const_string "simple_alu_imm") + (const_string "alu_shift")) + (const_string "load_byte")]) (set_attr "predicable" "yes") (set_attr "pool_range" "*,4096") (set_attr "neg_pool_range" "*,250")] @@ -581,7 +585,11 @@ (define_insn "*thumb2_zero_extendhisi2_v "@ uxth%?\\t%0, %1 ldr%(h%)\\t%0, %1" - [(set_attr "type" "alu_shift,load_byte") + [(set_attr_alternative "type" + [(if_then_else (eq_attr "tune" "cortexa7") + (const_string "simple_alu_imm") + (const_string "alu_shift")) + (const_string "load_byte")]) (set_attr "predicable" "yes") (set_attr "pool_range" "*,4096") (set_attr "neg_pool_range" "*,250")] @@ -594,7 +602,11 @@ (define_insn "thumb2_zero_extendqisi2_v6 "@ uxtb%(%)\\t%0, %1 ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2" - [(set_attr "type" "alu_shift,load_byte") + [(set_attr_alternative "type" + [(if_then_else (eq_attr "tune" "cortexa7") + (const_string "simple_alu_imm") + (const_string "alu_shift")) + (const_string "load_byte")]) (set_attr "predicable" "yes") (set_attr "pool_range" "*,4096") (set_attr "neg_pool_range" "*,250")] @@ -790,8 +802,8 @@ (define_insn "thumb2_addsi3_compare0" (define_insn "*thumb2_addsi3_compare0_scratch" [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV - (plus:SI (match_operand:SI 0 "s_register_operand" "l, r") - (match_operand:SI 1 "arm_add_operand" "lPv,rIL")) + (plus:SI (match_operand:SI 0 "s_register_operand" "l,l, r,r") + (match_operand:SI 1 "arm_add_operand" "Pv,l,IL,r")) (const_int 0)))] "TARGET_THUMB2" "* @@ -808,7 +820,8 @@ (define_insn "*thumb2_addsi3_compare0_sc return \"cmn\\t%0, %1\"; " [(set_attr "conds" "set") - (set_attr "length" "2,4")] + (set_attr "length" "2,2,4,4") + (set_attr "type" "simple_alu_imm,*,simple_alu_imm,*")] ) (define_insn "*thumb2_mulsi_short" diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index d48d4e66a6c827ec6d471a218a175537f038d798..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -77,7 +77,7 @@ (define_insn "*arm_movsi_vfp" } " [(set_attr "predicable" "yes") - (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores") + (set_attr "type" "*,*,simple_alu_imm,simple_alu_imm,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores") (set_attr "neon_type" "*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*") (set_attr "insn" "mov,mov,mvn,mov,*,*,*,*,*,*,*") (set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*")