Show patches with: Submitter = Jennifer Schmitz       |    State = Action Required       |    Archived = No       |   31 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[2/2] AArch64: Enable dispatch scheduling for Olympus core. [1/2] Haifa scheduler: Prevent splitting of fusion pairs in dispatch scheduling - - - - --- 2025-10-23 Jennifer Schmitz New
[1/2] Haifa scheduler: Prevent splitting of fusion pairs in dispatch scheduling [1/2] Haifa scheduler: Prevent splitting of fusion pairs in dispatch scheduling - - - - --- 2025-10-23 Jennifer Schmitz New
[PR121602] aarch64: Force vector when folding svmul with all-ones op1. [PR121602] aarch64: Force vector when folding svmul with all-ones op1. - - - - --- 2025-08-29 Jennifer Schmitz New
[2/2,PR121604] aarch64: Fold svbrka/b with ptrue predicate and operand to pfalse. [1/2,PR121604] aarch64: Fix folding of svbrka/b + svpmov_lane with pfalse arguments - - - - --- 2025-08-26 Jennifer Schmitz New
[1/2,PR121604] aarch64: Fix folding of svbrka/b + svpmov_lane with pfalse arguments [1/2,PR121604] aarch64: Fix folding of svbrka/b + svpmov_lane with pfalse arguments - - - - --- 2025-08-26 Jennifer Schmitz New
[PR121599] aarch64: Fix ICE when op2 is zero for SVE2 saturating add intrinsics. [PR121599] aarch64: Fix ICE when op2 is zero for SVE2 saturating add intrinsics. - - - - --- 2025-08-25 Jennifer Schmitz New
[3/3] AArch64: Enable dispatch scheduling for Neoverse V2. [1/3] AArch64: Annotate SVE instructions with new instruction attribute. - - - - --- 2025-07-29 Jennifer Schmitz New
[2/3] AArch64: Implement target hooks for dispatch scheduling. [1/3] AArch64: Annotate SVE instructions with new instruction attribute. - - - - --- 2025-07-29 Jennifer Schmitz New
[1/3] AArch64: Annotate SVE instructions with new instruction attribute. [1/3] AArch64: Annotate SVE instructions with new instruction attribute. - - - - --- 2025-07-29 Jennifer Schmitz New
aarch64: Add tuning model for Olympus core. aarch64: Add tuning model for Olympus core. - - - - --- 2025-07-25 Jennifer Schmitz New
[PR120276] regcprop: Replace partial_subreg_p by ordered_p && maybe_lt [PR120276] regcprop: Replace partial_subreg_p by ordered_p && maybe_lt - - - - --- 2025-05-16 Jennifer Schmitz New
[PR117978] AArch64: Fold SVE load/store with certain ptrue patterns to LDR/STR. [PR117978] AArch64: Fold SVE load/store with certain ptrue patterns to LDR/STR. - - - - --- 2025-05-02 Jennifer Schmitz New
AArch64: Optimize SVE loads/stores with ptrue predicates to unpredicated instructions. AArch64: Optimize SVE loads/stores with ptrue predicates to unpredicated instructions. - - - - --- 2025-04-25 Jennifer Schmitz New
AArch64: Fold LD1/ST1 with ptrue to LDR/STR for 128-bit VLS AArch64: Fold LD1/ST1 with ptrue to LDR/STR for 128-bit VLS - - - - --- 2025-04-25 Jennifer Schmitz New
aarch64: Optimize SVE extract last to Neon lane extract for 128-bit VLS. aarch64: Optimize SVE extract last to Neon lane extract for 128-bit VLS. - - - - --- 2025-04-25 Jennifer Schmitz New
[PR119706] aarch64: Add test case. [PR119706] aarch64: Add test case. - - - - --- 2025-04-10 Jennifer Schmitz New
[PR117704] testsuite: Fix test failure on x86_32 by adding -mfpmath=sse+387 [PR117704] testsuite: Fix test failure on x86_32 by adding -mfpmath=sse+387 - - - - --- 2024-11-28 Jennifer Schmitz New
[PR117093] testsuite: Move test pr117093.c into gcc.target/aarch64. [PR117093] testsuite: Move test pr117093.c into gcc.target/aarch64. - - - - --- 2024-11-18 Jennifer Schmitz New
SVE intrinsics: Fold svmul and svdiv by -1 to svneg for unsigned types SVE intrinsics: Fold svmul and svdiv by -1 to svneg for unsigned types - - - - --- 2024-11-11 Jennifer Schmitz New
[RFC,PR117093] match.pd: Fold vec_perm with view_convert [RFC,PR117093] match.pd: Fold vec_perm with view_convert - - - - --- 2024-11-05 Jennifer Schmitz New
[PR106329] SVE intrinsics: Fold calls with pfalse predicate. [PR106329] SVE intrinsics: Fold calls with pfalse predicate. - - - - --- 2024-10-31 Jennifer Schmitz New
SVE intrinsics: Fold svaba with op1 all zeros to svabd. SVE intrinsics: Fold svaba with op1 all zeros to svabd. - - - - --- 2024-10-24 Jennifer Schmitz New
testsuite: Add test directive checking removal of link_error testsuite: Add test directive checking removal of link_error - - - - --- 2024-10-22 Jennifer Schmitz New
match.pd: Add std::pow folding optimizations. match.pd: Add std::pow folding optimizations. - - - - --- 2024-10-18 Jennifer Schmitz New
SVE intrinsics: Fold svsra with op1 all zeros to svlsr/svasr. SVE intrinsics: Fold svsra with op1 all zeros to svlsr/svasr. - - - - --- 2024-10-18 Jennifer Schmitz New
SVE intrinsics: Add constant folding for svindex. SVE intrinsics: Add constant folding for svindex. - - - - --- 2024-10-16 Jennifer Schmitz New
SVE intrinsics: Add constant folding for svindex. SVE intrinsics: Add constant folding for svindex. - - - - --- 2024-10-16 Jennifer Schmitz New
SVE intrinsics: Fold division and multiplication by -1 to neg. SVE intrinsics: Fold division and multiplication by -1 to neg. - - - - --- 2024-10-15 Jennifer Schmitz New
SVE intrinsics: Add fold_active_lanes_to method to refactor svmul and svdiv. SVE intrinsics: Add fold_active_lanes_to method to refactor svmul and svdiv. - - - - --- 2024-10-15 Jennifer Schmitz New
SVE intrinsics: Fold svmul with constant power-of-2 operand to svlsl SVE intrinsics: Fold svmul with constant power-of-2 operand to svlsl - - - - --- 2024-10-11 Jennifer Schmitz New
[PR113816] AArch64: Use SIMD+GPR for logical vector reductions [PR113816] AArch64: Use SIMD+GPR for logical vector reductions - - - - --- 2024-10-10 Jennifer Schmitz New