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: Submitter =
Edwin Lu
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| 52 patches
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Apply
Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
[gcc-13,backport] RISC-V: Fix C23 (...) functions returning large aggregates [PR114175]
[gcc-13,backport] RISC-V: Fix C23 (...) functions returning large aggregates [PR114175]
1 - - -
-
-
-
2024-04-03
Edwin Lu
New
RISC-V: Fix C23 (...) functions returning large aggregates [PR114175]
RISC-V: Fix C23 (...) functions returning large aggregates [PR114175]
- - - -
-
-
-
2024-03-18
Edwin Lu
New
[V2] RISC-V: Update test expectancies with recent scheduler change
[V2] RISC-V: Update test expectancies with recent scheduler change
- - - -
-
-
-
2024-03-12
Edwin Lu
New
middle-end: Fix dominator information with loop duplication PR114197
middle-end: Fix dominator information with loop duplication PR114197
- - - -
-
-
-
2024-03-01
Edwin Lu
New
RISC-V: Update test expectancies with recent scheduler change
RISC-V: Update test expectancies with recent scheduler change
- - - -
-
-
-
2024-02-23
Edwin Lu
New
[V2] RISC-V: Specify mtune and march for PR113742
[V2] RISC-V: Specify mtune and march for PR113742
- - - -
-
-
-
2024-02-20
Edwin Lu
New
[V4,5/5] RISC-V: Enable assert for insn_has_dfa_reservation
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2024-02-15
Edwin Lu
New
[V4,4/5] RISC-V: Quick and simple fixes to testcases that break due to reordering
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2024-02-15
Edwin Lu
New
[V4,3/5] RISC-V: Use default cost model for insn scheduling
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2024-02-15
Edwin Lu
New
[V4,2/5] RISC-V: Add vector related pipelines
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2024-02-15
Edwin Lu
New
[V4,1/5] RISC-V: Add non-vector types to dfa pipelines
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2024-02-15
Edwin Lu
New
RISC-V: Set require-effective-target rv64 for PR113742
RISC-V: Set require-effective-target rv64 for PR113742
- - - -
-
-
-
2024-02-14
Edwin Lu
New
testsuite: Add support for scanning assembly with comparitor
testsuite: Add support for scanning assembly with comparitor
- - - -
-
-
-
2024-02-12
Edwin Lu
New
RISC-V: Add support for B standard extension
RISC-V: Add support for B standard extension
- - - -
-
-
-
2024-02-06
Edwin Lu
New
[V4,2/4] RISC-V: Add vector related pipelines
Untitled series #393042
- - - -
-
-
-
2024-01-31
Edwin Lu
New
RISC-V: Fix rvv intrinsic pragma tests dejagnu selector
RISC-V: Fix rvv intrinsic pragma tests dejagnu selector
- - 1 -
-
-
-
2024-01-29
Edwin Lu
New
[V3,4/4] RISC-V: Enable assert for insn_has_dfa_reservation
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2024-01-12
Edwin Lu
New
[V3,3/4] RISC-V: Use default cost model for insn scheduling
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2024-01-12
Edwin Lu
New
[V3,2/4] RISC-V: Add vector related pipelines
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2024-01-12
Edwin Lu
New
[V3,1/4] RISC-V: Add non-vector types to dfa pipelines
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2024-01-12
Edwin Lu
New
[V2,4/4,RFC] RISC-V: Enable assert for insn_has_dfa_reservation
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2024-01-10
Edwin Lu
New
[V2,3/4,RFC] RISC-V: Use default cost model for insn scheduling for tests affected in PR113249
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2024-01-10
Edwin Lu
New
[V2,2/4,RFC] RISC-V: Add vector related reservations
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2024-01-10
Edwin Lu
New
[V2,1/4,RFC] RISC-V: Add non-vector types to dfa pipelines
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2024-01-10
Edwin Lu
New
[3/3,RFC] RISC-V: Enable assert for insn_has_dfa_reservation
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2023-12-15
Edwin Lu
New
[2/3,RFC] RISC-V: Add vector related reservations
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2023-12-15
Edwin Lu
New
[1/3,RFC] RISC-V: Add non-vector types to pipelines
RISC-V: Associate typed insns to dfa reservation
- - - -
-
-
-
2023-12-15
Edwin Lu
New
[V3] RISC-V: XFAIL scan dump fails for autovec PR111311
[V3] RISC-V: XFAIL scan dump fails for autovec PR111311
- - - -
-
-
-
2023-12-13
Edwin Lu
New
[V2] RISC-V: XFAIL scan dump fails for autovec PR111311
[V2] RISC-V: XFAIL scan dump fails for autovec PR111311
- - - -
-
-
-
2023-12-08
Edwin Lu
New
RISC-V: XFAIL scan dump fails for autovec PR111311
RISC-V: XFAIL scan dump fails for autovec PR111311
- - - -
-
-
-
2023-12-07
Edwin Lu
New
RISC-V: Remove xfail from ssa-fre-3.c testcase
RISC-V: Remove xfail from ssa-fre-3.c testcase
- - 1 -
-
-
-
2023-12-06
Edwin Lu
New
RISC-V: Change unaligned fast/slow/avoid macros to misaligned [PR111557]
RISC-V: Change unaligned fast/slow/avoid macros to misaligned [PR111557]
- - - -
-
-
-
2023-11-15
Edwin Lu
New
RISC-V: Add check for types without insn reservations
RISC-V: Add check for types without insn reservations
- - - -
-
-
-
2023-11-01
Edwin Lu
New
[RFC] Make genautomata.cc output reflect insn-attr.h expectation:
[RFC] Make genautomata.cc output reflect insn-attr.h expectation:
- - - -
-
-
-
2023-10-31
Edwin Lu
New
[RFC] RISC-V: Handle new types in scheduling descriptions
[RFC] RISC-V: Handle new types in scheduling descriptions
- - - -
-
-
-
2023-10-09
Edwin Lu
New
RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert
RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert
- - - -
-
-
-
2023-09-11
Edwin Lu
New
[v2,2/5] RISC-V: Add Types for Un-Typed zc Instructions
RISC-V: Add Types to Untyped Instructions
- - - -
-
-
-
2023-09-08
Edwin Lu
New
[v2,1/5] RISC-V: Update Types for Vector Instructions
RISC-V: Add Types to Untyped Instructions
- - - -
-
-
-
2023-09-08
Edwin Lu
New
[5/5] RISC-V: Remove Assert Protecting Types
RISC-V: Add Types to Untyped Instructions
- - - -
-
-
-
2023-09-06
Edwin Lu
New
[4/5] RISC-V: Update Types for RISC-V Instructions
RISC-V: Add Types to Untyped Instructions
- - - -
-
-
-
2023-09-06
Edwin Lu
New
[3/5] RISC-V: Add Types to Un-Typed Zicond Instructions
RISC-V: Add Types to Untyped Instructions
- - - -
-
-
-
2023-09-06
Edwin Lu
New
[2/5] RISC-V: Add Types for Un-Typed zc Instructions
RISC-V: Add Types to Untyped Instructions
- - - -
-
-
-
2023-09-06
Edwin Lu
New
[1/5] RISC-V: Update Types for Vector Instructions
RISC-V: Add Types to Untyped Instructions
- - - -
-
-
-
2023-09-06
Edwin Lu
New
Add Types to Un-Typed Pic Instructions:
Add Types to Un-Typed Pic Instructions:
- - - -
-
-
-
2023-08-31
Edwin Lu
New
RISC-V Add Types to Un-Typed Thead Instructions:
RISC-V Add Types to Un-Typed Thead Instructions:
- - - -
-
-
-
2023-08-31
Edwin Lu
New
RISC-V: Add Types to Un-Typed Risc-v Instructions:
RISC-V: Add Types to Un-Typed Risc-v Instructions:
- - - -
-
-
-
2023-08-31
Edwin Lu
New
RISC-V: Add Types to Un-Typed Vector Instructions:
RISC-V: Add Types to Un-Typed Vector Instructions:
- - - -
-
-
-
2023-08-28
Edwin Lu
New
MAINTAINERS: Add myself to write after approval
MAINTAINERS: Add myself to write after approval
- - - -
-
-
-
2023-08-25
Edwin Lu
New
[V2] RISC-V: Add Types to Un-Typed Sync Instructions:
[V2] RISC-V: Add Types to Un-Typed Sync Instructions:
- - - -
-
-
-
2023-08-24
Edwin Lu
New
RISC-V: Add Types to Un-Typed Sync Instructions:
RISC-V: Add Types to Un-Typed Sync Instructions:
- - - -
-
-
-
2023-08-21
Edwin Lu
New
RISC-V: Add Types to Missing Bitmanip Instructions:
RISC-V: Add Types to Missing Bitmanip Instructions:
- - - -
-
-
-
2023-08-21
Edwin Lu
New
[V3] riscv: generate builtin macro for compilation with strict alignment:
[V3] riscv: generate builtin macro for compilation with strict alignment:
- - - -
-
-
-
2023-08-15
Edwin Lu
New