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: Submitter =
Li Xu
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| 52 patches
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Apply
Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
[v2] RISC-V: Add riscv_vector_cc function attribute
[v2] RISC-V: Add riscv_vector_cc function attribute
- - - -
-
-
-
2024-03-01
Li Xu
New
RISC-V: Add riscv_vector_cc function attribute
RISC-V: Add riscv_vector_cc function attribute
- - - -
-
-
-
2024-02-27
Li Xu
New
[v2] RISC-V: Bugfix for resolve_overloaded_builtin[PR113420]
[v2] RISC-V: Bugfix for resolve_overloaded_builtin[PR113420]
- - - -
-
-
-
2024-01-22
Li Xu
New
RISC-V: Bugfix for resolve_overloaded_builtin[PR113420]
RISC-V: Bugfix for resolve_overloaded_builtin[PR113420]
- - - -
-
-
-
2024-01-19
Li Xu
New
testsuite: Fix dump checks under different riscv-sim for RVV.
testsuite: Fix dump checks under different riscv-sim for RVV.
- - - -
-
-
-
2023-12-19
Li Xu
New
testsuite: Fix cpymem-2.c dump checks under different riscv-sim for RVV.
testsuite: Fix cpymem-2.c dump checks under different riscv-sim for RVV.
- - - -
-
-
-
2023-12-19
Li Xu
New
[v2] testsuite: Fix cpymem-1.c dump checks under different riscv-sim for RVV.
[v2] testsuite: Fix cpymem-1.c dump checks under different riscv-sim for RVV.
- - - -
-
-
-
2023-12-18
Li Xu
New
testsuite: Fix cpymem-1.c dump checks under different riscv-sim for RVV.
testsuite: Fix cpymem-1.c dump checks under different riscv-sim for RVV.
- - - -
-
-
-
2023-12-18
Li Xu
New
RISC-V: Add viota missed avl_type attribute
RISC-V: Add viota missed avl_type attribute
- - - -
-
-
-
2023-12-18
Li Xu
New
RISC-V: Remove useless modes
RISC-V: Remove useless modes
- - - -
-
-
-
2023-12-06
Li Xu
New
[v2] RISC-V: FAIL:g++.dg/torture/vshuf-v[2|4]di.C -Os (execution test) on RV32
[v2] RISC-V: FAIL:g++.dg/torture/vshuf-v[2|4]di.C -Os (execution test) on RV32
- - - -
-
-
-
2023-12-05
Li Xu
New
RISC-V: FAIL:g++.dg/torture/vshuf-v[2|4]di.C -Os (execution test) on RV32
RISC-V: FAIL:g++.dg/torture/vshuf-v[2|4]di.C -Os (execution test) on RV32
- - - -
-
-
-
2023-12-05
Li Xu
New
RISC-V: Add explicit braces to eliminate warning.
RISC-V: Add explicit braces to eliminate warning.
- - - -
-
-
-
2023-11-29
Li Xu
New
RISC-V: Implement -mmemcpy-strategy= options[PR112537]
RISC-V: Implement -mmemcpy-strategy= options[PR112537]
- - - -
-
-
-
2023-11-17
Li Xu
New
RISC-V: Eliminate unused parameter warning.
RISC-V: Eliminate unused parameter warning.
- - - -
-
-
-
2023-11-08
Li Xu
New
RISC-V: Support vcreate intrinsics for non-tuple types
RISC-V: Support vcreate intrinsics for non-tuple types
- - - -
-
-
-
2023-11-02
Li Xu
New
RISC-V: Support vundefine intrinsics for tuple types
RISC-V: Support vundefine intrinsics for tuple types
- - - -
-
-
-
2023-11-01
Li Xu
New
[v6] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic
[v6] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic
- - - -
-
-
-
2023-10-31
Li Xu
New
[V5] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic
[V5] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic
- - - -
-
-
-
2023-10-31
Li Xu
New
[V4] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic
[V4] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic
- - - -
-
-
-
2023-10-30
Li Xu
New
[v2] RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935]
[v2] RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935]
- - - -
-
-
-
2023-10-24
Li Xu
New
RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935]
RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935]
- - - -
-
-
-
2023-10-24
Li Xu
New
RISC-V: Fix scan-assembler-times of RVV test case
RISC-V: Fix scan-assembler-times of RVV test case
- - - -
-
-
-
2023-10-07
Li Xu
New
[v2] RISC-V: Bugfix for RTL check[PR111533]
[v2] RISC-V: Bugfix for RTL check[PR111533]
- - - -
-
-
-
2023-09-28
Li Xu
New
RISC-V: Bugfix for RTL check[PR111533]
RISC-V: Bugfix for RTL check[PR111533]
- - - -
-
-
-
2023-09-27
Li Xu
New
[V2] RISC-V: Optimization of vrgather.vv into vrgatherei16.vv[PR111451]
[V2] RISC-V: Optimization of vrgather.vv into vrgatherei16.vv[PR111451]
- - - -
-
-
-
2023-09-22
Li Xu
New
RISC-V: Optimization of vrgather.vv into vrgatherei16.vv[PR111451]
RISC-V: Optimization of vrgather.vv into vrgatherei16.vv[PR111451]
- - - -
-
-
-
2023-09-22
Li Xu
New
RISC-V: Optimized for strided load/store with stride == element width[PR111450]
RISC-V: Optimized for strided load/store with stride == element width[PR111450]
- - - -
-
-
-
2023-09-21
Li Xu
New
RISC-V: Remove phase 6 of vsetvl pass in GCC13[PR111412]
RISC-V: Remove phase 6 of vsetvl pass in GCC13[PR111412]
- - - -
-
-
-
2023-09-18
Li Xu
New
[v3] RISC-V: Elimilate warning in class vcreate
[v3] RISC-V: Elimilate warning in class vcreate
- - - -
-
-
-
2023-09-12
Li Xu
New
[v2] RISC-V: Elimilate warning in class vcreate
[v2] RISC-V: Elimilate warning in class vcreate
- - - -
-
-
-
2023-09-12
Li Xu
New
RISC-V: Elimilate warning
RISC-V: Elimilate warning
- - - -
-
-
-
2023-09-12
Li Xu
New
RISC-V: Add vcreate intrinsics for RVV tuple types
RISC-V: Add vcreate intrinsics for RVV tuple types
- - - -
-
-
-
2023-09-12
Li Xu
New
RISCV: Fix PR111074 [GCC13 BUG]
RISCV: Fix PR111074 [GCC13 BUG]
- - - -
-
-
-
2023-08-22
Li Xu
New
[committed] MAINTAINERS: Add myself to write after approval
[committed] MAINTAINERS: Add myself to write after approval
- - - -
-
-
-
2023-07-31
Li Xu
New
RISC-V: Remove vxrm parameter for vsadd[u] and vssub[u]
RISC-V: Remove vxrm parameter for vsadd[u] and vssub[u]
- - - -
-
-
-
2023-07-28
Li Xu
New
RISC-V: Fix vector tuple intrinsic
RISC-V: Fix vector tuple intrinsic
- - - -
-
-
-
2023-07-26
Li Xu
New
[v2] RISC-V: Fix vector tuple intrinsic
[v2] RISC-V: Fix vector tuple intrinsic
- - - -
-
-
-
2023-07-26
Li Xu
New
RISC-V: Fix vector tuple intrinsic
RISC-V: Fix vector tuple intrinsic
- - - -
-
-
-
2023-07-26
Li Xu
New
RISCV: Fix local_eliminate_vsetvl_insn bug in VSETVL PASS[PR110560]
RISCV: Fix local_eliminate_vsetvl_insn bug in VSETVL PASS[PR110560]
- - - -
-
-
-
2023-07-07
Li Xu
New
Extend streamer_mode_table size to MACHINE_MODE_BITSIZE.
Extend streamer_mode_table size to MACHINE_MODE_BITSIZE.
- - - -
-
-
-
2023-06-27
Li Xu
New
[v2] RISC-V: fix expand function of vlmul_ext RVV intrinsic
[v2] RISC-V: fix expand function of vlmul_ext RVV intrinsic
- - - -
-
-
-
2023-06-25
Li Xu
New
RISC-V: force arg and target to reg rtx under -O0
RISC-V: force arg and target to reg rtx under -O0
- - - -
-
-
-
2023-06-25
Li Xu
New
[v2] RISC-V: Set the natural size of constant vector mask modes to one RVV data vector.
[v2] RISC-V: Set the natural size of constant vector mask modes to one RVV data vector.
- - - -
-
-
-
2023-06-20
Li Xu
New
RISC-V: Set the natural size of constant vector mask modes to one RVV data vector.
RISC-V: Set the natural size of constant vector mask modes to one RVV data vector.
- - - -
-
-
-
2023-06-20
Li Xu
New
[v2] RISC-V: Fix VWEXTF iterator requirement
[v2] RISC-V: Fix VWEXTF iterator requirement
- - - -
-
-
-
2023-06-19
Li Xu
New
RISC-V: Fix iterator requirement
RISC-V: Fix iterator requirement
- - - -
-
-
-
2023-06-19
Li Xu
New
RISC-V: Fix 'REQUIREMENT' for machine_mode 'MODE' in vector-iterators.md.
RISC-V: Fix 'REQUIREMENT' for machine_mode 'MODE' in vector-iterators.md.
- - - -
-
-
-
2023-06-05
Li Xu
New
[V2] RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instructions satisfying REG_P(operand[1])…
[V2] RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instructions satisfying REG_P(operand[1])…
- - - -
-
-
-
2023-05-10
Li Xu
New
RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instructions satisfying REG_P(operand[1]) in -…
RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instructions satisfying REG_P(operand[1]) in -…
- - - -
-
-
-
2023-05-10
Li Xu
New
RISC-V: Fix typo
RISC-V: Fix typo
- - - -
-
-
-
2023-04-04
Li Xu
New
RISC-V: Fix typo
RISC-V: Fix typo
- - - -
-
-
-
2023-04-03
Li Xu
New