Show patches with: Submitter = Jeffrey Law       |    State = Action Required       |    Archived = No       |   159 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[to-be-committed] Fix various RISC-V testsuite regressions after volatile patch [to-be-committed] Fix various RISC-V testsuite regressions after volatile patch - - - - --- 2025-12-17 Jeffrey Law New
[to-be-committed,RISC-V] Add cpu and tuning structures for spacemit-x60 design [to-be-committed,RISC-V] Add cpu and tuning structures for spacemit-x60 design - - - - --- 2025-11-17 Jeffrey Law New
[to-be-committed,RISC-V] Avoid most calls to gen_extend_insn [to-be-committed,RISC-V] Avoid most calls to gen_extend_insn - - - - --- 2025-11-15 Jeffrey Law New
[committed,RISC-V] Drop scan-tests of marginal value [committed,RISC-V] Drop scan-tests of marginal value - - - - --- 2025-11-14 Jeffrey Law New
[to-be-committed,RISC-V] Improve detection of packw [to-be-committed,RISC-V] Improve detection of packw - - - - --- 2025-11-11 Jeffrey Law New
[committed,RISC-V] Add testcase for shifted truthvalue [committed,RISC-V] Add testcase for shifted truthvalue - - - - --- 2025-11-08 Jeffrey Law New
[to-be-committed,RISC-V] Ignore useless zero-initialization in conditional move sequence costing [to-be-committed,RISC-V] Ignore useless zero-initialization in conditional move sequence costing - - - - --- 2025-11-06 Jeffrey Law New
[to-be-committed,PR,rtl-optimization/122536] Fix guard against variable bit extracts in RTL simplif… [to-be-committed,PR,rtl-optimization/122536] Fix guard against variable bit extracts in RTL simplif… - - - - --- 2025-11-03 Jeffrey Law New
[to-be-committed,RISC-V,PR,tree-optimization/52345] Optimize testing multiple booleans [to-be-committed,RISC-V,PR,tree-optimization/52345] Optimize testing multiple booleans - - - - --- 2025-11-02 Jeffrey Law New
[RISC-V] Expose sign extension for 32 bit rotates by constant values on rv64 [RISC-V] Expose sign extension for 32 bit rotates by constant values on rv64 - - - - --- 2025-11-02 Jeffrey Law New
[committed] Fix minor RISC-V testsuite failure [committed] Fix minor RISC-V testsuite failure - - - - --- 2025-10-20 Jeffrey Law New
[to-be-committed,RISC-V] Improve subword atomic patterns in sync.md [to-be-committed,RISC-V] Improve subword atomic patterns in sync.md - - - - --- 2025-10-10 Jeffrey Law New
[to-be-committed,RISC-V,PR,rtl-optimization/121937] Don't call neg_poly_int_rtx with a vector mode [to-be-committed,RISC-V,PR,rtl-optimization/121937] Don't call neg_poly_int_rtx with a vector mode - - - - --- 2025-10-02 Jeffrey Law New
[to-be-committed,PR,tree-optimization/58727] Don't over-simplify constants [to-be-committed,PR,tree-optimization/58727] Don't over-simplify constants - - - - --- 2025-09-14 Jeffrey Law New
[RFA] Fix latent LRA bug [RFA] Fix latent LRA bug - - - - --- 2025-09-12 Jeffrey Law New
[committed,RISC-V] Fix ordering of pipeline models [committed,RISC-V] Fix ordering of pipeline models - - - - --- 2025-09-07 Jeffrey Law New
[committed,RISC-V] Adjust recently added test [committed,RISC-V] Adjust recently added test - - - - --- 2025-09-06 Jeffrey Law New
[RISC-V,PR,target/121213] Avoid unnecessary constant load in amoswap [RISC-V,PR,target/121213] Avoid unnecessary constant load in amoswap - - - - --- 2025-08-31 Jeffrey Law New
[to-be-committed,RISC-V] Improve initial RTL generation for SImode adds on rv64 [to-be-committed,RISC-V] Improve initial RTL generation for SImode adds on rv64 - - - - --- 2025-08-30 Jeffrey Law New
[to-be-committed,PR,target/121548] Avoid bogus index into recog operand cache [to-be-committed,PR,target/121548] Avoid bogus index into recog operand cache - - - - --- 2025-08-29 Jeffrey Law New
[committed] More RISC-V testsuite hygiene [committed] More RISC-V testsuite hygiene - - - - --- 2025-08-27 Jeffrey Law New
[committed] Fix invalid right shift count with recent ifcvt changes [committed] Fix invalid right shift count with recent ifcvt changes - - - - --- 2025-08-25 Jeffrey Law New
[to-be-committed,PR,target/119275,RISC-V] Avoid calling gen_lowpart in cases where it would ICE [to-be-committed,PR,target/119275,RISC-V] Avoid calling gen_lowpart in cases where it would ICE - - - - --- 2025-08-14 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/121531] Cover missing insn types in p400 and p600 scheduler models [to-be-committed,RISC-V,PR,target/121531] Cover missing insn types in p400 and p600 scheduler models - - - - --- 2025-08-13 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/121160] Avoid bogus force_reg call [to-be-committed,RISC-V,PR,target/121160] Avoid bogus force_reg call - - - - --- 2025-08-13 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/121113] Handle HFmode in various insn reservations [to-be-committed,RISC-V,PR,target/121113] Handle HFmode in various insn reservations - - - - --- 2025-08-12 Jeffrey Law New
[to-be-committed,RISC-V] Improve initial code generation for addsi/adddi [to-be-committed,RISC-V] Improve initial code generation for addsi/adddi - - - - --- 2025-08-11 Jeffrey Law New
[to-be-committed,RISC-V] Detect new fusions for RISC-V [to-be-committed,RISC-V] Detect new fusions for RISC-V - - - - --- 2025-07-09 Jeffrey Law New
[to-be-committed,RISC-V] Add basic instrumentation to fusion detection [to-be-committed,RISC-V] Add basic instrumentation to fusion detection - - - - --- 2025-07-03 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/118886] Refine when two insns are signaled as fusion candidates [to-be-committed,RISC-V,PR,target/118886] Refine when two insns are signaled as fusion candidates - - - - --- 2025-07-03 Jeffrey Law New
[committed,PR,rtl-optimization/120242] Fix SUBREG_PROMOTED_VAR_P after ext-dce's actions [committed,PR,rtl-optimization/120242] Fix SUBREG_PROMOTED_VAR_P after ext-dce's actions - - - - --- 2025-07-02 Jeffrey Law New
[to-be-committed,RISC-V] Enable more if-conversion on RISC-V [to-be-committed,RISC-V] Enable more if-conversion on RISC-V - - - - --- 2025-06-08 Jeffrey Law New
[to-be-committed,RISC-V] Improve sequences to generate -1, 1 in some cases. [to-be-committed,RISC-V] Improve sequences to generate -1, 1 in some cases. - - - - --- 2025-06-05 Jeffrey Law New
[to-be-committed,RISC-V] shift+and+shift for logical and synthesis [to-be-committed,RISC-V] shift+and+shift for logical and synthesis - - - - --- 2025-05-24 Jeffrey Law New
[to-be-committed,RISC-V] Clear high or low bits using shift pairs [to-be-committed,RISC-V] Clear high or low bits using shift pairs - - - - --- 2025-05-21 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/120368] Fix 32bit shift on rv64 [to-be-committed,RISC-V,PR,target/120368] Fix 32bit shift on rv64 - - - - --- 2025-05-21 Jeffrey Law New
[to-be-committed,RISC-V] Infrastructure of synthesizing logical AND with constant [to-be-committed,RISC-V] Infrastructure of synthesizing logical AND with constant - - - - --- 2025-05-20 Jeffrey Law New
[to-be-committed,RISC-V,PR,middle-end/114512] Recognize more bext idioms for RISC-V [to-be-committed,RISC-V,PR,middle-end/114512] Recognize more bext idioms for RISC-V - - - - --- 2025-05-06 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/119865] Don't free ggc allocated memory [to-be-committed,RISC-V,PR,target/119865] Don't free ggc allocated memory - - - - --- 2025-04-19 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/118410] Improve code generation for some logical ops [to-be-committed,RISC-V,PR,target/118410] Improve code generation for some logical ops - - - - --- 2025-04-19 Jeffrey Law New
[committed,RISC-V] Fix testsuite fallout from recent changes [committed,RISC-V] Fix testsuite fallout from recent changes - - - - --- 2025-04-11 Jeffrey Law New
[committed,RISC-V] Adjust expected output for rvv test [committed,RISC-V] Adjust expected output for rvv test - - - - --- 2025-04-09 Jeffrey Law New
[RISC-V] Fix another unreported code quality regression [RISC-V] Fix another unreported code quality regression - - - - --- 2025-03-18 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/118934] Fix ICE in RISC-V long branch supportvi !$ [to-be-committed,RISC-V,PR,target/118934] Fix ICE in RISC-V long branch supportvi !$ - - - - --- 2025-03-02 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/118146] Fix ICE for unsupported modes [to-be-committed,RISC-V,PR,target/118146] Fix ICE for unsupported modes - - - - --- 2025-02-09 Jeffrey Law New
[committed] Disable ABS instruction on bfin port [committed] Disable ABS instruction on bfin port - - - - --- 2025-02-05 Jeffrey Law New
[committed,PR,testsuite/116860] Testsuite adjustment for recently added tests [committed,PR,testsuite/116860] Testsuite adjustment for recently added tests - - - - --- 2025-01-30 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/116256] Fix latent regression in pattern to associate arithmetic … [to-be-committed,RISC-V,PR,target/116256] Fix latent regression in pattern to associate arithmetic … - - - - --- 2025-01-20 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/116308] Fix generation of initial RTL for atomics [to-be-committed,RISC-V,PR,target/116308] Fix generation of initial RTL for atomics - - - - --- 2025-01-18 Jeffrey Law New
[committed,RISC-V,PR,target/118170] Add HF div/sqrt reservation [committed,RISC-V,PR,target/118170] Add HF div/sqrt reservation - - - - --- 2025-01-15 Jeffrey Law New
[committed] Fix testsuite expectations for RVV after recent change [committed] Fix testsuite expectations for RVV after recent change - - - - --- 2025-01-07 Jeffrey Law New
[to-be-committed,PR,target/116720] Fix test for valid mempair operands [to-be-committed,PR,target/116720] Fix test for valid mempair operands - - - - --- 2024-12-29 Jeffrey Law New
[committed,PR,tree-optimization/117895] Fix sparc libgo build failure with CRC opts enabled [committed,PR,tree-optimization/117895] Fix sparc libgo build failure with CRC opts enabled - - - - --- 2024-12-06 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/117690] Add missing shift in constant synthesis [to-be-committed,RISC-V,PR,target/117690] Add missing shift in constant synthesis - - - - --- 2024-11-21 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/116590] Avoid emitting multiple instructions from fmacc patterns [to-be-committed,RISC-V,PR,target/116590] Avoid emitting multiple instructions from fmacc patterns - - - - --- 2024-11-20 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/117649] Fix branch on masked values splitter [to-be-committed,RISC-V,PR,target/117649] Fix branch on masked values splitter - - - - --- 2024-11-19 Jeffrey Law New
[committed] Improve ext-dce's ability to eliminate more extensions [committed] Improve ext-dce's ability to eliminate more extensions - - - - --- 2024-11-18 Jeffrey Law New
[RFC,RISC-V] Add target dependent pass to optimize related permutation constants [RFC,RISC-V] Add target dependent pass to optimize related permutation constants - - - - --- 2024-11-14 Jeffrey Law New
[RFA/RFC,RISC-V] Fix type on vector move pattern [RFA/RFC,RISC-V] Fix type on vector move pattern - - - - --- 2024-11-12 Jeffrey Law New
[to-be-committed,RISC-V] Drop undesirable two instruction macc alternatives [to-be-committed,RISC-V] Drop undesirable two instruction macc alternatives - - - - --- 2024-11-11 Jeffrey Law New
[to-be-committed,RISC-V] Aggressively hoist VXRM assignments [to-be-committed,RISC-V] Aggressively hoist VXRM assignments - - - - --- 2024-10-29 Jeffrey Law New
[to-be-committed,RISC-V] Avoid unnecessary extensions when value is already extended [to-be-committed,RISC-V] Avoid unnecessary extensions when value is already extended - - - - --- 2024-10-12 Jeffrey Law New
[to-be-committed,RISC-V] Slightly improve broadcasting small constants into vectors [to-be-committed,RISC-V] Slightly improve broadcasting small constants into vectors - - - - --- 2024-10-11 Jeffrey Law New
[to-be-committed,RISC-V] Add splitters to restore condops generation after recent phiopt changes [to-be-committed,RISC-V] Add splitters to restore condops generation after recent phiopt changes - - - - --- 2024-10-03 Jeffrey Law New
[committed,RISC-V] Fix scan test output after recent path-splitting changes [committed,RISC-V] Fix scan test output after recent path-splitting changes - - - - --- 2024-09-04 Jeffrey Law New
[committed] Fix assembly scan for RISC-V VLS tests [committed] Fix assembly scan for RISC-V VLS tests - - - - --- 2024-08-25 Jeffrey Law New
[committed] Turn off late-combine for a few risc-v specific tests [committed] Turn off late-combine for a few risc-v specific tests - - - - --- 2024-08-25 Jeffrey Law New
[committed,rtl-optimization/116244] Don't create bogus regs in alter_subreg [committed,rtl-optimization/116244] Don't create bogus regs in alter_subreg - - - - --- 2024-08-12 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/116283] Fix split code for recent Zbs improvements with masked bi… [to-be-committed,RISC-V,PR,target/116283] Fix split code for recent Zbs improvements with masked bi… - - - - --- 2024-08-09 Jeffrey Law New
[RFA,PR,rtl-optimization/116136] Fix previously latent SUBREG simplification bug [RFA,PR,rtl-optimization/116136] Fix previously latent SUBREG simplification bug - - - - --- 2024-07-30 Jeffrey Law New
[committed,rtl-optimization/116037] Explicitly track if a destination was skipped in ext-dce [committed,rtl-optimization/116037] Explicitly track if a destination was skipped in ext-dce - - - - --- 2024-07-24 Jeffrey Law New
[committed,4/n,PR,rtl-optimization/115877] Correct SUBREG handling in a destination [committed,4/n,PR,rtl-optimization/115877] Correct SUBREG handling in a destination - - - - --- 2024-07-22 Jeffrey Law New
[committed,PR,rtl-optimization/115877] Fix livein computation for ext-dce [committed,PR,rtl-optimization/115877] Fix livein computation for ext-dce - - - - --- 2024-07-21 Jeffrey Law New
[committed,PR,rtl-optimization/115876] Fix one of two ubsan reported issues in new ext-dce.cc code [committed,PR,rtl-optimization/115876] Fix one of two ubsan reported issues in new ext-dce.cc code - - - - --- 2024-07-12 Jeffrey Law New
[committed] Fix m68k bootstrap segfault with late-combine [committed] Fix m68k bootstrap segfault with late-combine - - - - --- 2024-07-12 Jeffrey Law New
[to-be-committed,RISC-V] Eliminate unnecessary sign extension after inlined str[n]cmp [to-be-committed,RISC-V] Eliminate unnecessary sign extension after inlined str[n]cmp - - - - --- 2024-07-10 Jeffrey Law New
[to-be-committed,RISC-V] Improve bset generation for another case [to-be-committed,RISC-V] Improve bset generation for another case - - - - --- 2024-07-09 Jeffrey Law New
[to-be-committed,RISC-V,V2] Minor cleanup/improvement to bset/binv patterns [to-be-committed,RISC-V,V2] Minor cleanup/improvement to bset/binv patterns - - - - --- 2024-06-19 Jeffrey Law New
[to-be-committed,RISC-V] Improve (1 << N) | C for rv64 [to-be-committed,RISC-V] Improve (1 << N) | C for rv64 - - - - --- 2024-06-10 Jeffrey Law New
[to-be-committed,RISC-V] Use bext for extracting a bit into a SImode object [to-be-committed,RISC-V] Use bext for extracting a bit into a SImode object - - - - --- 2024-06-09 Jeffrey Law New
[to-be-committed,RISC-V] Use pack to handle repeating constants [to-be-committed,RISC-V] Use pack to handle repeating constants - - - - --- 2024-05-29 Jeffrey Law New
[to-be-committed,RISC-V] Some basic patterns for zbkb code generation [to-be-committed,RISC-V] Some basic patterns for zbkb code generation - - - - --- 2024-05-27 Jeffrey Law New
[to-be-committed,RISC-V] Reassociate constants in logical ops [to-be-committed,RISC-V] Reassociate constants in logical ops - - - - --- 2024-05-26 Jeffrey Law New
[to-be-committed,RISC-V] Try inverting for constant synthesis [to-be-committed,RISC-V] Try inverting for constant synthesis - - - - --- 2024-05-26 Jeffrey Law New
[committed,v2] More logical op simplifications in simplify-rtx.cc [committed,v2] More logical op simplifications in simplify-rtx.cc - - - - --- 2024-05-25 Jeffrey Law New
[to-be-committed,RISC-V] Generate nearby constant, then adjust to our final desired constant [to-be-committed,RISC-V] Generate nearby constant, then adjust to our final desired constant - - - - --- 2024-05-25 Jeffrey Law New
[to-be-committed,RISC-V] Use bclri in constant synthesis [to-be-committed,RISC-V] Use bclri in constant synthesis - - - - --- 2024-05-23 Jeffrey Law New
[to-be-committed,RISC-V] Eliminate redundant bitmanip operation [to-be-committed,RISC-V] Eliminate redundant bitmanip operation - - - - --- 2024-05-19 Jeffrey Law New
[to-be-committed,RISC-V,PR,target/115142] Do not create invalidate shift-add insn [to-be-committed,RISC-V,PR,target/115142] Do not create invalidate shift-add insn - - - - --- 2024-05-19 Jeffrey Law New
[to-be-committed,PR,target/115142] Do not create invalidate shift-add insn [to-be-committed,PR,target/115142] Do not create invalidate shift-add insn - - - - --- 2024-05-18 Jeffrey Law New
[to-be-committed,RISC-V] Improve some shift-add sequences [to-be-committed,RISC-V] Improve some shift-add sequences - - - - --- 2024-05-15 Jeffrey Law New
[committed] Fix rv32 issues with recent zicboz work [committed] Fix rv32 issues with recent zicboz work - - - - --- 2024-05-15 Jeffrey Law New
[to-be-committed,RISC-V] Remove redundant AND in shift-add sequence [to-be-committed,RISC-V] Remove redundant AND in shift-add sequence - - - - --- 2024-05-14 Jeffrey Law New
[to-be-committed,RISC-V] Improve AND with some constants [to-be-committed,RISC-V] Improve AND with some constants - - - - --- 2024-05-13 Jeffrey Law New
[to-be-committed,RISC-V] Improve single inverted bit extraction - v3 [to-be-committed,RISC-V] Improve single inverted bit extraction - v3 - - - - --- 2024-05-13 Jeffrey Law New
[to-be-committed,RISC-V] Improve single inverted bit extraction - v2 [to-be-committed,RISC-V] Improve single inverted bit extraction - v2 - - - - --- 2024-05-12 Jeffrey Law New
[to-be-committed,RISC-V] Improve single inverted bit extraction [to-be-committed,RISC-V] Improve single inverted bit extraction - - - - --- 2024-05-12 Jeffrey Law New
[to-be-committed,RISC-V] Improve usage of slli.uw in constant synthesis [to-be-committed,RISC-V] Improve usage of slli.uw in constant synthesis - - - - --- 2024-05-12 Jeffrey Law New
[to-be-committed] RISC-V Fix minor regression in synthesis WRT bseti usage [to-be-committed] RISC-V Fix minor regression in synthesis WRT bseti usage - - - - --- 2024-05-12 Jeffrey Law New
[RISC-V] Use shNadd for constant synthesis [RISC-V] Use shNadd for constant synthesis - - - - --- 2024-05-10 Jeffrey Law New
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