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Wed, 14 Feb 2024 17:11:24 -0800 (PST) Received: from ewlu.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 21-20020a170902c25500b001d8f12b0009sm60611plg.293.2024.02.14.17.11.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Feb 2024 17:11:24 -0800 (PST) From: Edwin Lu To: gcc-patches@gcc.gnu.org Cc: gnu-toolchain@rivosinc.com, Edwin Lu Subject: [PATCH V4 0/5] RISC-V: Associate typed insns to dfa reservation Date: Wed, 14 Feb 2024 17:11:16 -0800 Message-Id: <20240215011121.2434218-1-ewlu@rivosinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-5.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Previous version (V3 23cd2961bd2ff63583f46e3499a07bd54491d45c) was reverted. Updates all tune insn reservation pipelines to cover all types defined by define_attr "type" in riscv.md. Creates new vector insn reservation pipelines in new file generic-vector-ooo.md which has separate automaton vector_ooo where all reservations are mapped to. This allows all tunes to share a common vector model for now as we make large changes to the vector cost model. (https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642511.html) Disables pipeline scheduling for some tests with scan dump failures when using -mtune=generic-ooo. Updates test cases that were failing due to simple insn reordering to match new code generation Enables assert that all insn types must be associated with a dfa pipeline reservation --- V2: - Update non-vector insn types and add new pipelines - Add -fno-schedule-insn -fno-schedule-insn2 to some test cases V3: - Separate vector pipelines to separate file which all tunes have access to V4: - Add insn reservations to sifive-p400 and sifive-p600 series - Update test cases with new code generation --- Edwin Lu (5): RISC-V: Add non-vector types to dfa pipelines RISC-V: Add vector related pipelines RISC-V: Use default cost model for insn scheduling RISC-V: Quick and simple fixes to testcases that break due to reordering RISC-V: Enable assert for insn_has_dfa_reservation gcc/config/riscv/generic-ooo.md | 140 ++--------------- gcc/config/riscv/generic-vector-ooo.md | 143 ++++++++++++++++++ gcc/config/riscv/generic.md | 20 ++- gcc/config/riscv/riscv.cc | 2 - gcc/config/riscv/riscv.md | 17 +-- gcc/config/riscv/sifive-7.md | 17 ++- gcc/config/riscv/sifive-p400.md | 10 +- gcc/config/riscv/sifive-p600.md | 10 +- gcc/config/riscv/vector.md | 2 +- gcc/config/riscv/zc.md | 96 ++++++------ .../g++.target/riscv/rvv/base/bug-1.C | 2 + .../riscv/rvv/autovec/reduc/reduc_call-2.c | 2 + .../rvv/autovec/vls/calling-convention-1.c | 27 +++- .../rvv/autovec/vls/calling-convention-2.c | 23 ++- .../rvv/autovec/vls/calling-convention-3.c | 18 ++- .../rvv/autovec/vls/calling-convention-4.c | 12 +- .../rvv/autovec/vls/calling-convention-5.c | 22 ++- .../rvv/autovec/vls/calling-convention-6.c | 17 +++ .../rvv/autovec/vls/calling-convention-7.c | 12 +- .../riscv/rvv/base/binop_vx_constraint-102.c | 2 + .../riscv/rvv/base/binop_vx_constraint-108.c | 2 + .../riscv/rvv/base/binop_vx_constraint-114.c | 2 + .../riscv/rvv/base/binop_vx_constraint-119.c | 2 + .../riscv/rvv/base/binop_vx_constraint-12.c | 2 +- .../riscv/rvv/base/binop_vx_constraint-16.c | 2 +- .../riscv/rvv/base/binop_vx_constraint-17.c | 2 +- .../riscv/rvv/base/binop_vx_constraint-19.c | 2 +- .../riscv/rvv/base/binop_vx_constraint-21.c | 2 +- .../riscv/rvv/base/binop_vx_constraint-23.c | 2 +- .../riscv/rvv/base/binop_vx_constraint-25.c | 2 +- .../riscv/rvv/base/binop_vx_constraint-27.c | 2 +- .../riscv/rvv/base/binop_vx_constraint-29.c | 2 +- .../riscv/rvv/base/binop_vx_constraint-31.c | 2 +- .../riscv/rvv/base/binop_vx_constraint-33.c | 2 +- .../riscv/rvv/base/binop_vx_constraint-35.c | 2 +- .../riscv/rvv/base/binop_vx_constraint-4.c | 2 +- .../riscv/rvv/base/binop_vx_constraint-40.c | 2 +- .../riscv/rvv/base/binop_vx_constraint-44.c | 2 +- .../riscv/rvv/base/binop_vx_constraint-50.c | 2 + .../riscv/rvv/base/binop_vx_constraint-56.c | 2 + .../riscv/rvv/base/binop_vx_constraint-62.c | 2 + .../riscv/rvv/base/binop_vx_constraint-68.c | 2 + .../riscv/rvv/base/binop_vx_constraint-74.c | 2 + .../riscv/rvv/base/binop_vx_constraint-79.c | 2 + .../riscv/rvv/base/binop_vx_constraint-8.c | 2 +- .../riscv/rvv/base/binop_vx_constraint-84.c | 2 + .../riscv/rvv/base/binop_vx_constraint-90.c | 2 + .../riscv/rvv/base/binop_vx_constraint-96.c | 2 + .../rvv/base/float-point-dynamic-frm-30.c | 2 + .../gcc.target/riscv/rvv/base/pr108185-1.c | 2 + .../gcc.target/riscv/rvv/base/pr108185-2.c | 2 + .../gcc.target/riscv/rvv/base/pr108185-3.c | 2 + .../gcc.target/riscv/rvv/base/pr108185-4.c | 2 + .../gcc.target/riscv/rvv/base/pr108185-5.c | 2 + .../gcc.target/riscv/rvv/base/pr108185-6.c | 2 + .../gcc.target/riscv/rvv/base/pr108185-7.c | 2 + .../riscv/rvv/base/shift_vx_constraint-1.c | 3 +- .../riscv/rvv/vsetvl/avl_single-107.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/pr111037-3.c | 2 + .../riscv/rvv/vsetvl/vlmax_back_prop-28.c | 2 + .../riscv/rvv/vsetvl/vlmax_back_prop-29.c | 2 + .../riscv/rvv/vsetvl/vlmax_back_prop-32.c | 2 + .../riscv/rvv/vsetvl/vlmax_back_prop-33.c | 2 + .../riscv/rvv/vsetvl/vlmax_single_block-17.c | 2 + .../riscv/rvv/vsetvl/vlmax_single_block-18.c | 2 + .../riscv/rvv/vsetvl/vlmax_single_block-19.c | 2 + .../riscv/rvv/vsetvl/vlmax_switch_vtype-10.c | 2 + .../riscv/rvv/vsetvl/vlmax_switch_vtype-11.c | 2 + .../riscv/rvv/vsetvl/vlmax_switch_vtype-12.c | 2 + .../riscv/rvv/vsetvl/vlmax_switch_vtype-4.c | 2 + .../riscv/rvv/vsetvl/vlmax_switch_vtype-5.c | 2 + .../riscv/rvv/vsetvl/vlmax_switch_vtype-6.c | 2 + .../riscv/rvv/vsetvl/vlmax_switch_vtype-7.c | 2 + .../riscv/rvv/vsetvl/vlmax_switch_vtype-8.c | 2 + .../riscv/rvv/vsetvl/vlmax_switch_vtype-9.c | 2 + gcc/testsuite/gfortran.dg/vect/vect-8.f90 | 2 + 76 files changed, 483 insertions(+), 224 deletions(-) create mode 100644 gcc/config/riscv/generic-vector-ooo.md