[0/5] LoongArch: Add -mrecip option support

Message ID	20231128032938.17202-1-xujiahao@loongson.cn
Headers	show Return-Path: <gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org> DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8AB69385B516 From: Jiahao Xu <xujiahao@loongson.cn> To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, chenglulu@loongson.cn, xuchenghua@loongson.cn, Jiahao Xu <xujiahao@loongson.cn> Subject: [PATCH 0/5] LoongArch: Add -mrecip option support Date: Tue, 28 Nov 2023 11:29:33 +0800 Message-Id: <20231128032938.17202-1-xujiahao@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=114.242.206.163; envelope-from=xujiahao@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org
Series	LoongArch: Add -mrecip option support \| expand [0/5] LoongArch: Add -mrecip option support [1/5] LoongArch: Add support for approximate instructions. [2/5] LoongArch: Use standard pattern name for xvfrsqrt/vfrsqrt instructions. [3/5] LoongArch: Redefine pattern for xvfrecip/vfrecip instructions. [4/5] LoongArch: New options -mrecip and -mrecip= with ffast-math. [5/5] LoongArch: Vectorized loop unrolling is not performed on divf/sqrtf/rsqrtf with turns on -mre…

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20231128032938.17202-1-xujiahao@loongson.cn

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From: Jiahao Xu <xujiahao@loongson.cn>
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 xuchenghua@loongson.cn, Jiahao Xu <xujiahao@loongson.cn>
Subject: [PATCH 0/5] LoongArch: Add -mrecip option support
Date: Tue, 28 Nov 2023 11:29:33 +0800
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Series

LoongArch: Add -mrecip option support | expand

Message

Jiahao Xu Nov. 28, 2023, 3:29 a.m. UTC

LoongArch V1.1 instructions adds support for approximate instructions, which are utilized along
with additional Newton-Raphson steps implement single precision floating-point division, square
root and reciprocal square root operations for better throughput. Control the generation of
approximate instructions by implementing '-mrecip' and '-mrecip='.

Jiahao Xu (5):
  LoongArch: Add support for approximate instructions.
  LoongArch: Use standard pattern name for xvfrsqrt/vfrsqrt
    instructions.
  LoongArch: Redefine pattern for xvfrecip/vfrecip instructions.
  LoongArch: New options -mrecip and -mrecip= with ffast-math.
  LoongArch: Vectorized loop unrolling is not performed on
    divf/sqrtf/rsqrtf with turns on -mrecip.

 gcc/config/loongarch/genopts/loongarch.opt.in |  11 +
 gcc/config/loongarch/lasx.md                  |  89 ++++++-
 gcc/config/loongarch/lasxintrin.h             |  32 +++
 gcc/config/loongarch/loongarch-builtins.cc    |  32 +++
 gcc/config/loongarch/loongarch-protos.h       |   2 +
 gcc/config/loongarch/loongarch.cc             | 252 +++++++++++++++++-
 gcc/config/loongarch/loongarch.h              |  18 ++
 gcc/config/loongarch/loongarch.md             | 104 ++++++--
 gcc/config/loongarch/loongarch.opt            |  11 +
 gcc/config/loongarch/lsx.md                   |  89 ++++++-
 gcc/config/loongarch/lsxintrin.h              |  32 +++
 gcc/config/loongarch/predicates.md            |   8 +
 gcc/doc/invoke.texi                           |  52 ++++
 .../gcc.target/loongarch/recip-divf.c         |   9 +
 .../gcc.target/loongarch/recip-sqrtf.c        |  23 ++
 .../loongarch/vector/lasx/lasx-recip-divf.c   |  12 +
 .../loongarch/vector/lasx/lasx-recip-sqrtf.c  |  28 ++
 .../loongarch/vector/lsx/lsx-recip-divf.c     |  12 +
 .../loongarch/vector/lsx/lsx-recip-sqrtf.c    |  28 ++
 19 files changed, 803 insertions(+), 41 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/recip-divf.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/recip-sqrtf.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-recip-divf.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-recip-sqrtf.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-recip-divf.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-recip-sqrtf.c