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[v1,0/3] RISC-V: Improve sequences with shifted zero-extended operands

Message ID 20220524214703.4022737-1-philipp.tomsich@vrull.eu
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Series RISC-V: Improve sequences with shifted zero-extended operands | expand

Message

Philipp Tomsich May 24, 2022, 9:47 p.m. UTC 
Code-generation currently misses some opportunities for optimized
sequences when zero-extension is combined with shifts.


Philipp Tomsich (3):
  RISC-V: add consecutive_bits_operand predicate
  RISC-V: Split slli+sh[123]add.uw opportunities to avoid zext.w
  RISC-V: Replace zero_extendsidi2_shifted with generalized split

 gcc/config/riscv/bitmanip.md               | 44 ++++++++++++++++++++++
 gcc/config/riscv/predicates.md             | 11 ++++++
 gcc/config/riscv/riscv.md                  | 37 +++++++++---------
 gcc/testsuite/gcc.target/riscv/zba-shadd.c | 13 +++++++
 4 files changed, 88 insertions(+), 17 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shadd.c