diff mbox

[v3,04/10] acpi: dbg2: add SBBR compliance tests

Message ID 1503497389-5224-1-git-send-email-Sakar.Arora@arm.com
State Accepted
Headers show

Commit Message

Sakar Arora Aug. 23, 2017, 2:09 p.m. UTC 
From: Rajat Goyal <Rajat.Goyal@arm.com>

Server Base Boot Requirements (SBBR) specification is intended for SBSA-
compliant 64-bit ARMv8 servers.
It defines the base firmware requirements for out-of-box support of any
ARM SBSA-compatible Operating System or hypervisor.
The requirements in this specification are expected to be minimal yet
complete for booting a multi-core ARMv8 server platform, while leaving
plenty of room for OEM or ODM innovations and design details.
For more information, download the SBBR specification here:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0044b/index.html

This change introduces test cases as per SBBR specification to dbg2
table.

Signed-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com>
Signed-off-by: Rajat Goyal <Rajat.Goyal@arm.com>
Signed-off-by: Sakar Arora <Sakar.Arora@arm.com>
---
 src/acpi/dbg2/dbg2.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 48 insertions(+), 2 deletions(-)

Comments

Colin Ian King Aug. 23, 2017, 2:20 p.m. UTC | #1 
On 23/08/17 15:09, Sakar Arora wrote:
> From: Rajat Goyal <Rajat.Goyal@arm.com>
> 
> Server Base Boot Requirements (SBBR) specification is intended for SBSA-
> compliant 64-bit ARMv8 servers.
> It defines the base firmware requirements for out-of-box support of any
> ARM SBSA-compatible Operating System or hypervisor.
> The requirements in this specification are expected to be minimal yet
> complete for booting a multi-core ARMv8 server platform, while leaving
> plenty of room for OEM or ODM innovations and design details.
> For more information, download the SBBR specification here:
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0044b/index.html
> 
> This change introduces test cases as per SBBR specification to dbg2
> table.
> 
> Signed-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com>
> Signed-off-by: Rajat Goyal <Rajat.Goyal@arm.com>
> Signed-off-by: Sakar Arora <Sakar.Arora@arm.com>
> ---
>  src/acpi/dbg2/dbg2.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++--
>  1 file changed, 48 insertions(+), 2 deletions(-)
> 
> diff --git a/src/acpi/dbg2/dbg2.c b/src/acpi/dbg2/dbg2.c
> index e6f6f09..f760bd8 100644
> --- a/src/acpi/dbg2/dbg2.c
> +++ b/src/acpi/dbg2/dbg2.c
> @@ -30,6 +30,9 @@
>  
>  #include "fwts_acpi_object_eval.h"
>  
> +#define SBBR_DBG2_PORT_SERIAL   0x8000
> +#define SBBR_DBG2_ARM_SBSA_UART 0x000E
> +
>  static fwts_acpi_table_info *table;
>  
>  static int dbg2_init(fwts_framework *fw)
> @@ -39,10 +42,52 @@ static int dbg2_init(fwts_framework *fw)
>  		return FWTS_ERROR;
>  	}
>  	if (table == NULL || (table && table->length == 0)) {
> -		fwts_log_error(fw, "ACPI DBG2 table does not exist, skipping test");
> +		if (fw->flags & FWTS_FLAG_TEST_SBBR) {
> +			fwts_log_error(fw,
> +				"ACPI DBG2 table does not exist");
> +			return FWTS_ERROR;
> +		} else {
> +			fwts_log_error(fw,
> +				"ACPI DBG2 table does not exist, skipping test");
> +			return FWTS_SKIP;
> +		}
> +	}
> +
> +	return FWTS_OK;
> +}
> +
> +static int dbg2_test2(fwts_framework *fw)
> +{
> +	uint32_t i;
> +
> +	if (!(fw->flags & FWTS_FLAG_TEST_SBBR))
>  		return FWTS_SKIP;
> +
> +	fwts_acpi_table_dbg2 *dbg2 = (fwts_acpi_table_dbg2 *)table->data;
> +	fwts_acpi_table_dbg2_info *info;
> +
> +	info = (fwts_acpi_table_dbg2_info *)(table->data + dbg2->info_offset);
> +
> +	for (i = 0; i < dbg2->info_count; i++) {
> +		if ((uint8_t*)&info->length >= ((uint8_t*)table + table->length))
> +			break;
> +		if (((uint8_t*)info + info->length) >= ((uint8_t*)table + table->length))
> +			break;
> +		if ((info->port_type == SBBR_DBG2_PORT_SERIAL) &&
> +		(info->port_subtype == SBBR_DBG2_ARM_SBSA_UART)) {
> +			fwts_passed(fw,
> +				"DBG2 provides a standard serial debug "
> +				"port and describes ARM SBSA Generic UART");
> +			return FWTS_OK;
> +		}
> +
> +		/* ..and onto the next info structure .. */
> +		info = (fwts_acpi_table_dbg2_info *)((uint8_t *)info +
> +			info->length);
>  	}
>  
> +	fwts_failed(fw, LOG_LEVEL_CRITICAL, "dbg2_sbsa_uart:",
> +			"DBG2 provides a non standard debug port");
>  	return FWTS_OK;
>  }
>  
> @@ -343,6 +388,7 @@ done:
>  
>  static fwts_framework_minor_test dbg2_tests[] = {
>  	{ dbg2_test1, "DBG2 (Debug Port Table 2) test." },
> +	{ dbg2_test2, "DBG2 ARM SBSA Generic UART test," },
>  	{ NULL, NULL }
>  };
>  
> @@ -352,6 +398,6 @@ static fwts_framework_ops dbg2_ops = {
>  	.minor_tests = dbg2_tests
>  };
>  
> -FWTS_REGISTER("dbg2", &dbg2_ops, FWTS_TEST_ANYTIME, FWTS_FLAG_BATCH | FWTS_FLAG_TEST_ACPI)
> +FWTS_REGISTER("dbg2", &dbg2_ops, FWTS_TEST_ANYTIME, FWTS_FLAG_BATCH | FWTS_FLAG_TEST_ACPI | FWTS_FLAG_TEST_SBBR)
>  
>  #endif
> 

Acked-by: Colin Ian King <colin.king@canonical.com>
Alex Hung Aug. 23, 2017, 6:53 p.m. UTC | #2 
On 2017-08-23 07:09 AM, Sakar Arora wrote:
> From: Rajat Goyal <Rajat.Goyal@arm.com>
> 
> Server Base Boot Requirements (SBBR) specification is intended for SBSA-
> compliant 64-bit ARMv8 servers.
> It defines the base firmware requirements for out-of-box support of any
> ARM SBSA-compatible Operating System or hypervisor.
> The requirements in this specification are expected to be minimal yet
> complete for booting a multi-core ARMv8 server platform, while leaving
> plenty of room for OEM or ODM innovations and design details.
> For more information, download the SBBR specification here:
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0044b/index.html
> 
> This change introduces test cases as per SBBR specification to dbg2
> table.
> 
> Signed-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com>
> Signed-off-by: Rajat Goyal <Rajat.Goyal@arm.com>
> Signed-off-by: Sakar Arora <Sakar.Arora@arm.com>
> ---
>   src/acpi/dbg2/dbg2.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++--
>   1 file changed, 48 insertions(+), 2 deletions(-)
> 
> diff --git a/src/acpi/dbg2/dbg2.c b/src/acpi/dbg2/dbg2.c
> index e6f6f09..f760bd8 100644
> --- a/src/acpi/dbg2/dbg2.c
> +++ b/src/acpi/dbg2/dbg2.c
> @@ -30,6 +30,9 @@
>   
>   #include "fwts_acpi_object_eval.h"
>   
> +#define SBBR_DBG2_PORT_SERIAL   0x8000
> +#define SBBR_DBG2_ARM_SBSA_UART 0x000E
> +
>   static fwts_acpi_table_info *table;
>   
>   static int dbg2_init(fwts_framework *fw)
> @@ -39,10 +42,52 @@ static int dbg2_init(fwts_framework *fw)
>   		return FWTS_ERROR;
>   	}
>   	if (table == NULL || (table && table->length == 0)) {
> -		fwts_log_error(fw, "ACPI DBG2 table does not exist, skipping test");
> +		if (fw->flags & FWTS_FLAG_TEST_SBBR) {
> +			fwts_log_error(fw,
> +				"ACPI DBG2 table does not exist");
> +			return FWTS_ERROR;
> +		} else {
> +			fwts_log_error(fw,
> +				"ACPI DBG2 table does not exist, skipping test");
> +			return FWTS_SKIP;
> +		}
> +	}
> +
> +	return FWTS_OK;
> +}
> +
> +static int dbg2_test2(fwts_framework *fw)
> +{
> +	uint32_t i;
> +
> +	if (!(fw->flags & FWTS_FLAG_TEST_SBBR))
>   		return FWTS_SKIP;
> +
> +	fwts_acpi_table_dbg2 *dbg2 = (fwts_acpi_table_dbg2 *)table->data;
> +	fwts_acpi_table_dbg2_info *info;
> +
> +	info = (fwts_acpi_table_dbg2_info *)(table->data + dbg2->info_offset);
> +
> +	for (i = 0; i < dbg2->info_count; i++) {
> +		if ((uint8_t*)&info->length >= ((uint8_t*)table + table->length))
> +			break;
> +		if (((uint8_t*)info + info->length) >= ((uint8_t*)table + table->length))
> +			break;
> +		if ((info->port_type == SBBR_DBG2_PORT_SERIAL) &&
> +		(info->port_subtype == SBBR_DBG2_ARM_SBSA_UART)) {
> +			fwts_passed(fw,
> +				"DBG2 provides a standard serial debug "
> +				"port and describes ARM SBSA Generic UART");
> +			return FWTS_OK;
> +		}
> +
> +		/* ..and onto the next info structure .. */
> +		info = (fwts_acpi_table_dbg2_info *)((uint8_t *)info +
> +			info->length);
>   	}
>   
> +	fwts_failed(fw, LOG_LEVEL_CRITICAL, "dbg2_sbsa_uart:",
> +			"DBG2 provides a non standard debug port");
>   	return FWTS_OK;
>   }
>   
> @@ -343,6 +388,7 @@ done:
>   
>   static fwts_framework_minor_test dbg2_tests[] = {
>   	{ dbg2_test1, "DBG2 (Debug Port Table 2) test." },
> +	{ dbg2_test2, "DBG2 ARM SBSA Generic UART test," },
>   	{ NULL, NULL }
>   };
>   
> @@ -352,6 +398,6 @@ static fwts_framework_ops dbg2_ops = {
>   	.minor_tests = dbg2_tests
>   };
>   
> -FWTS_REGISTER("dbg2", &dbg2_ops, FWTS_TEST_ANYTIME, FWTS_FLAG_BATCH | FWTS_FLAG_TEST_ACPI)
> +FWTS_REGISTER("dbg2", &dbg2_ops, FWTS_TEST_ANYTIME, FWTS_FLAG_BATCH | FWTS_FLAG_TEST_ACPI | FWTS_FLAG_TEST_SBBR)
>   
>   #endif
> 

Acked-by: Alex Hung <alex.hung@canonical.com>
diff mbox

Patch

diff --git a/src/acpi/dbg2/dbg2.c b/src/acpi/dbg2/dbg2.c
index e6f6f09..f760bd8 100644
--- a/src/acpi/dbg2/dbg2.c
+++ b/src/acpi/dbg2/dbg2.c
@@ -30,6 +30,9 @@ 
 
 #include "fwts_acpi_object_eval.h"
 
+#define SBBR_DBG2_PORT_SERIAL   0x8000
+#define SBBR_DBG2_ARM_SBSA_UART 0x000E
+
 static fwts_acpi_table_info *table;
 
 static int dbg2_init(fwts_framework *fw)
@@ -39,10 +42,52 @@  static int dbg2_init(fwts_framework *fw)
 		return FWTS_ERROR;
 	}
 	if (table == NULL || (table && table->length == 0)) {
-		fwts_log_error(fw, "ACPI DBG2 table does not exist, skipping test");
+		if (fw->flags & FWTS_FLAG_TEST_SBBR) {
+			fwts_log_error(fw,
+				"ACPI DBG2 table does not exist");
+			return FWTS_ERROR;
+		} else {
+			fwts_log_error(fw,
+				"ACPI DBG2 table does not exist, skipping test");
+			return FWTS_SKIP;
+		}
+	}
+
+	return FWTS_OK;
+}
+
+static int dbg2_test2(fwts_framework *fw)
+{
+	uint32_t i;
+
+	if (!(fw->flags & FWTS_FLAG_TEST_SBBR))
 		return FWTS_SKIP;
+
+	fwts_acpi_table_dbg2 *dbg2 = (fwts_acpi_table_dbg2 *)table->data;
+	fwts_acpi_table_dbg2_info *info;
+
+	info = (fwts_acpi_table_dbg2_info *)(table->data + dbg2->info_offset);
+
+	for (i = 0; i < dbg2->info_count; i++) {
+		if ((uint8_t*)&info->length >= ((uint8_t*)table + table->length))
+			break;
+		if (((uint8_t*)info + info->length) >= ((uint8_t*)table + table->length))
+			break;
+		if ((info->port_type == SBBR_DBG2_PORT_SERIAL) &&
+		(info->port_subtype == SBBR_DBG2_ARM_SBSA_UART)) {
+			fwts_passed(fw,
+				"DBG2 provides a standard serial debug "
+				"port and describes ARM SBSA Generic UART");
+			return FWTS_OK;
+		}
+
+		/* ..and onto the next info structure .. */
+		info = (fwts_acpi_table_dbg2_info *)((uint8_t *)info +
+			info->length);
 	}
 
+	fwts_failed(fw, LOG_LEVEL_CRITICAL, "dbg2_sbsa_uart:",
+			"DBG2 provides a non standard debug port");
 	return FWTS_OK;
 }
 
@@ -343,6 +388,7 @@  done:
 
 static fwts_framework_minor_test dbg2_tests[] = {
 	{ dbg2_test1, "DBG2 (Debug Port Table 2) test." },
+	{ dbg2_test2, "DBG2 ARM SBSA Generic UART test," },
 	{ NULL, NULL }
 };
 
@@ -352,6 +398,6 @@  static fwts_framework_ops dbg2_ops = {
 	.minor_tests = dbg2_tests
 };
 
-FWTS_REGISTER("dbg2", &dbg2_ops, FWTS_TEST_ANYTIME, FWTS_FLAG_BATCH | FWTS_FLAG_TEST_ACPI)
+FWTS_REGISTER("dbg2", &dbg2_ops, FWTS_TEST_ANYTIME, FWTS_FLAG_BATCH | FWTS_FLAG_TEST_ACPI | FWTS_FLAG_TEST_SBBR)
 
 #endif