From patchwork Tue Sep 13 02:11:41 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Tommy.Lo" X-Patchwork-Id: 669861 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3sYylw4X9Nz9stY for ; Wed, 14 Sep 2016 20:42:04 +1000 (AEST) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1bk7cT-00015H-BM; Wed, 14 Sep 2016 12:40:45 +0200 Received: from acledge1.advantech.com.tw ([61.58.41.197]) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1bjdCa-0004x6-1W for flashrom@flashrom.org; Tue, 13 Sep 2016 04:12:15 +0200 Received: from ACLMS1.ADVANTECH.COM.TW ([172.20.1.75]) by acledge1.advantech.com.tw (8.14.7/8.14.7) with ESMTP id u8D2BmhR001529 for ; Tue, 13 Sep 2016 10:11:48 +0800 Received: from aclht3.ADVANTECH.CORP (unverified [172.20.1.12]) by ACLMS1.ADVANTECH.COM.TW (Clearswift SMTPRS 5.6.0) with ESMTP id for ; Tue, 13 Sep 2016 10:11:42 +0800 Received: from taipei08.ADVANTECH.CORP (172.20.0.235) by aclht3.ADVANTECH.CORP (172.20.1.12) with Microsoft SMTP Server (TLS) id 8.3.406.0; Tue, 13 Sep 2016 10:11:42 +0800 From: "Tommy.Lo" To: "flashrom@flashrom.org" Thread-Topic: [flashrom][Patch]ignore-read-error Thread-Index: AdIJqkBZIJ896IwHRbqTawKad/kvxwDuRsIw Date: Tue, 13 Sep 2016 02:11:41 +0000 Message-ID: References: <70c3ecdc9e8046a18849c1dd91987efe@taipei09.ADVANTECH.CORP> In-Reply-To: <70c3ecdc9e8046a18849c1dd91987efe@taipei09.ADVANTECH.CORP> Accept-Language: zh-TW, en-US Content-Language: zh-TW X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [172.17.10.68] MIME-Version: 1.0 X-StopIT: No X-Spam-Score: -7.8 (-------) X-Mailman-Approved-At: Wed, 14 Sep 2016 12:40:43 +0200 Subject: [flashrom] [Patch]ignore-read-error X-BeenThere: flashrom@flashrom.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: flashrom discussion and development mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Oakley.Ding" Errors-To: flashrom-bounces@flashrom.org Sender: "flashrom" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff Dear Maintainers , This patch is for the following description: Transaction is failed and errors are shown when flashrom try to read region that locked by Intel ME. This patch simply disable code to check error (will read 0xff) then flashrom will continue to read the rest. And only ignore the error when read op. It will output a warning message to stderr like: Transaction (READ) error at address 0x001000-0x7fffff, ignored To avoid a lot of similar error messages, it shows error at end of locked region. Thanks! Sign-off-by: Tommy Lo < tommy.lo@advantech.com.tw > Index: ichspi.c =================================================================== --- ichspi.c (revision 1955) +++ ichspi.c (working copy) @@ -178,6 +178,9 @@ static void *ich_spibar = NULL; +/* keep last addr of read error */ +static uint32_t last_read_warn_addr = 0xFFFFFFFF; + typedef struct _OPCODE { uint8_t opcode; //This commands spi opcode uint8_t spi_type; //This commands spi type @@ -946,14 +949,38 @@ /* FIXME make sure we do not needlessly cause transaction errors. */ temp32 = REGREAD32(ICH9_REG_SSFS); if (temp32 & SSFS_FCERR) { - msg_perr("Transaction error!\n"); - prettyprint_ich9_reg_ssfs(temp32); - prettyprint_ich9_reg_ssfc(temp32); - /* keep reserved bits */ - temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; - /* Clear the transaction error. */ - REGWRITE32(ICH9_REG_SSFS, temp32 | SSFS_FCERR); - return 1; + if (ichspi_lock && op.spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) { + /* keep reserved bits */ + temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; + /* Clear the transaction error. */ + REGWRITE32(ICH9_REG_SSFS, temp32 | SSFS_FCERR); + if (last_read_warn_addr != 0xFFFFFFFF) { + if (last_read_warn_addr == (offset - 1)) { + /* continuing */ + last_read_warn_addr = offset + datalength - 1; + } else { + msg_pdbg("-0x%06x, ignored\n", last_read_warn_addr); + last_read_warn_addr = 0xFFFFFFFF; + } + } else { + msg_pdbg("Transaction (READ) error at address 0x%06x", offset); + last_read_warn_addr = offset + datalength - 1; + } + } else { + prettyprint_ich9_reg_ssfs(temp32); + prettyprint_ich9_reg_ssfc(temp32); + /* keep reserved bits */ + temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; + /* Clear the transaction error. */ + REGWRITE32(ICH9_REG_SSFS, temp32 | SSFS_FCERR); + msg_perr("Transaction error!\n"); + return 1; + } + } else { + if (last_read_warn_addr != 0xFFFFFFFF) { + msg_pdbg("-0x%06x, ignored\n", last_read_warn_addr); + last_read_warn_addr = 0xFFFFFFFF; + } } if ((!write_cmd) && (datalength != 0))