From patchwork Thu Jul 28 22:36:21 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Tauner X-Patchwork-Id: 653895 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3s0mwZ3l0cz9sXx for ; Fri, 29 Jul 2016 08:38:22 +1000 (AEST) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1bStvx-0000v9-TR; Fri, 29 Jul 2016 00:37:41 +0200 Received: from mail2.student.tuwien.ac.at ([193.170.74.22]) by mail.coreboot.org with esmtps (TLSv1:DHE-RSA-AES256-SHA:256) (Exim 4.86_2) (envelope-from ) id 1bStvh-0000ta-ET for flashrom@flashrom.org; Fri, 29 Jul 2016 00:37:39 +0200 Received: from localhost.localdomain (chello080109083031.10.15.vie.surfer.at [80.109.83.31]) (authenticated bits=0) by mail2.student.tuwien.ac.at (8.13.8/8.13.8) with ESMTP id u6SMbGnb021360 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=NO); Fri, 29 Jul 2016 00:37:17 +0200 From: Stefan Tauner To: peter.ma@intel.com Date: Fri, 29 Jul 2016 00:36:21 +0200 Message-Id: <20160728223621.15074-1-stefan.tauner@alumni.tuwien.ac.at> X-Mailer: git-send-email 2.9.0.rc2.8.ga28705d In-Reply-To: <64D69DFCDAFF694EB6A483F4A19BEAFC0AEEF182@ORSMSX105.amr.corp.intel.com> References: <64D69DFCDAFF694EB6A483F4A19BEAFC0AEEF182@ORSMSX105.amr.corp.intel.com> X-Spam-Score: -0.1 (/) Subject: [flashrom] [PATCH] Add support for Micron N25Q016..3E X-BeenThere: flashrom@flashrom.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: flashrom discussion and development mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: flashrom@flashrom.org MIME-Version: 1.0 Errors-To: flashrom-bounces@flashrom.org Sender: "flashrom" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff This kind of chip seems to be behind Altera's EPCQ16 that is used to store configuration of FPGAs on some boards. No official datasheet matching the chip is available. The chip definition bases on the datasheet of the EPCQ16 and other Micron chips of the same familiy. Its existence and functionality via SFDP was reported by Peter Ma. Signed-off-by: Stefan Tauner On Thu, 28 Jul 2016 19:59:59 +0000 "Ma, Peter" wrote: > I just received a new set of boards with the Altera EPCQ16 that we discussed before. Something odd happened: I would use flashrom and it would do the usual "SFDP-capable chip" (2048 kB, SPI). > > But on subsequent tries (even after re-boots), flashrom is coming back with: > Found ST flash chip "unknown ST SPI chip" (0 kB, SPI) > > Have any idea as to what could be going wrong? Not exactly, no. Apparently something you did changed the chip's reaction to the SFDP query opcode or something similar. You could try lowering the SPI frequency and look for a changed behavior while probing for SFDP. If that fails you could also try the attached patch that adds a chip definition that should work for your variation as well. --- flashchips.c | 39 ++++++++++++++++++++++++++++++++++++++- flashchips.h | 2 ++ 2 files changed, 40 insertions(+), 1 deletion(-) diff --git a/flashchips.c b/flashchips.c index 40b6b8e..30c50ca 100644 --- a/flashchips.c +++ b/flashchips.c @@ -9505,7 +9505,7 @@ const struct flashchip flashchips[] = { { .vendor = "Micron/Numonyx/ST", - .name = "N25Q016", + .name = "N25Q016..1E", .bustype = BUS_SPI, .manufacture_id = ST_ID, .model_id = ST_N25Q016__1E, @@ -9542,6 +9542,43 @@ const struct flashchip flashchips[] = { { .vendor = "Micron/Numonyx/ST", + .name = "N25Q016..3E", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q016__3E, + .total_size = 2048, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 64} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Micron/Numonyx/ST", .name = "N25Q032..1E", .bustype = BUS_SPI, .manufacture_id = ST_ID, diff --git a/flashchips.h b/flashchips.h index 9ffb30f..7dfe985 100644 --- a/flashchips.h +++ b/flashchips.h @@ -839,6 +839,8 @@ #define ST_MT28GU256___2 0x8904 #define ST_MT28GU512___1 0x887E #define ST_MT28GU512___2 0x8881 +/* The N25Q family is also used by Altera in its EPCQ series. */ +#define ST_N25Q016__3E 0xBA15 /* N25Q016, 3.0V, (uniform sectors expected) */ #define ST_N25Q016__1E 0xBB15 /* N25Q016, 1.8V, (uniform sectors expected) */ #define ST_N25Q032__3E 0xBA16 /* N25Q032, 3.0V, (uniform sectors expected) */ #define ST_N25Q032__1E 0xBB16 /* N25Q032, 1.8V, (uniform sectors expected) */