From patchwork Thu Nov 4 09:32:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sander Vanheule X-Patchwork-Id: 1550814 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=svanheule.net header.i=@svanheule.net header.a=rsa-sha256 header.s=mail1707 header.b=3ciw58Hs; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HlJMB5HD8z9sRR for ; Thu, 4 Nov 2021 20:32:22 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230495AbhKDJe6 (ORCPT ); Thu, 4 Nov 2021 05:34:58 -0400 Received: from polaris.svanheule.net ([84.16.241.116]:37918 "EHLO polaris.svanheule.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230472AbhKDJe5 (ORCPT ); Thu, 4 Nov 2021 05:34:57 -0400 Received: from terra.local.svanheule.net (unknown [IPv6:2a02:a03f:eafe:c901:bf08:f0c1:3ec1:1bfc]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id BC73A26C288; Thu, 4 Nov 2021 10:32:18 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1636018339; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/pod07EU/dO9gkwNUDL95GTzJ3wqD5S57lkIkq6n7Uw=; b=3ciw58Hsyv4n23taCmdzziLIV/hMzdbVsPzzoj5L6WGr7vmT5QHKjZQZ5Y1FLn/WzFah6p dBjAmNYpc6QpsGhY92bDUQqLB+skpZpRlctdmJXGTL7MBuGb2pVrlWUn3oqCha6jPd1P4I V9qNv6N6wmtlgxYAR49tSAIv7tKah6xSnbJT4o/xAgu4H/D+V/ZP0GIfIBObJFqiifysca wB0lqxUBO78mhsWMfDbQqrsqpYs/lXn2WCvBv5Psz/lwrj/BKJcD/in+CrSH2fgQb+9EeA 2gdnBUPCMnC0JDrmSi0HjINlyVMEaVzNg6g7BCsKYi9E5j71mUyuyVwe9/wp3w== From: Sander Vanheule To: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org Cc: Wim Van Sebroeck , Guenter Roeck , Rob Herring , linux-kernel@vger.kernel.org, Sander Vanheule , Rob Herring Subject: [PATCH v3 1/2] dt-bindings: watchdog: Realtek Otto WDT binding Date: Thu, 4 Nov 2021 10:32:12 +0100 Message-Id: <62b3d83fcd56c46d070e7f2a9387fef2a2789499.1636018117.git.sander@svanheule.net> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a binding description for Realtek's watchdog timer as found on several of their MIPS-based SoCs (codenamed Otto), such as the RTL838x, RTL839x, and RTL930x series of switch SoCs. Signed-off-by: Sander Vanheule Reviewed-by: Rob Herring Reviewed-by: Guenter Roeck --- v2: - add realtek,rtl9300-wdt compatible - make interrupts property required - add Rob's Reviewed-by tag --- .../bindings/watchdog/realtek,otto-wdt.yaml | 91 +++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/realtek,otto-wdt.yaml diff --git a/Documentation/devicetree/bindings/watchdog/realtek,otto-wdt.yaml b/Documentation/devicetree/bindings/watchdog/realtek,otto-wdt.yaml new file mode 100644 index 000000000000..11b220a5e0f6 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/realtek,otto-wdt.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/realtek,otto-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek Otto watchdog timer + +maintainers: + - Sander Vanheule + +description: | + The timer has two timeout phases. Both phases have a maximum duration of 32 + prescaled clock ticks, which is ca. 43s with a bus clock of 200MHz. The + minimum duration of each phase is one tick. Each phase can trigger an + interrupt, although the phase 2 interrupt will occur with the system reset. + - Phase 1: During this phase, the WDT can be pinged to reset the timeout. + - Phase 2: Starts after phase 1 has timed out, and only serves to give the + system some time to clean up, or notify others that it's going to reset. + During this phase, pinging the WDT has no effect, and a reset is + unavoidable, unless the WDT is disabled. + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + enum: + - realtek,rtl8380-wdt + - realtek,rtl8390-wdt + - realtek,rtl9300-wdt + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + items: + - description: interrupt specifier for pretimeout + - description: interrupt specifier for timeout + + interrupt-names: + items: + - const: phase1 + - const: phase2 + + realtek,reset-mode: + $ref: /schemas/types.yaml#/definitions/string + description: | + Specify how the system is reset after a timeout. Defaults to "cpu" if + left unspecified. + oneOf: + - description: Reset the entire chip + const: soc + - description: | + Reset the CPU and IPsec engine, but leave other peripherals untouched + const: cpu + - description: | + Reset the execution pointer, but don't actually reset any hardware + const: software + +required: + - compatible + - reg + - clocks + - interrupts + +unevaluatedProperties: false + +dependencies: + interrupts: [ interrupt-names ] + +examples: + - | + watchdog: watchdog@3150 { + compatible = "realtek,rtl8380-wdt"; + reg = <0x3150 0xc>; + + realtek,reset-mode = "soc"; + + clocks = <&lxbus_clock>; + timeout-sec = <20>; + + interrupt-parent = <&rtlintc>; + interrupt-names = "phase1", "phase2"; + interrupts = <19>, <18>; + }; + +...