From patchwork Mon Feb 23 22:07:30 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 442679 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id B1ACF140188 for ; Tue, 24 Feb 2015 09:08:04 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752868AbbBWWHe (ORCPT ); Mon, 23 Feb 2015 17:07:34 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:47155 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752155AbbBWWHd (ORCPT ); Mon, 23 Feb 2015 17:07:33 -0500 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 5B50D1409FA; Mon, 23 Feb 2015 22:07:32 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id 48FD5140C24; Mon, 23 Feb 2015 22:07:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-caf-smtp.dmz.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=ALL_TRUSTED,BAYES_00 autolearn=ham version=3.3.1 Received: from [10.134.64.202] (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: sboyd@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 0C7FD1409FA; Mon, 23 Feb 2015 22:07:30 +0000 (UTC) Message-ID: <54EBA4A2.1050607@codeaurora.org> Date: Mon, 23 Feb 2015 14:07:30 -0800 From: Stephen Boyd User-Agent: Mozilla/5.0 (X11; Linux i686 on x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.4.0 MIME-Version: 1.0 To: Arnd Bergmann , Mathieu Olivari CC: mark.rutland@arm.com, devicetree@vger.kernel.org, linux@arm.linux.org.uk, linux-watchdog@vger.kernel.org, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, corbet@lwn.net, linux-kernel@vger.kernel.org, standby24x7@gmail.com, wim@iguana.be, robh+dt@kernel.org, galak@codeaurora.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 0/3] arm: msm: Use timer DT node for qcom watchdog config References: <1424485176-8348-1-git-send-email-mathieu@codeaurora.org> <5879121.Ud0l5ICsCF@wuerfel> In-Reply-To: <5879121.Ud0l5ICsCF@wuerfel> X-Virus-Scanned: ClamAV using ClamSMTP Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 02/23/15 13:35, Arnd Bergmann wrote: > On Friday 20 February 2015 18:19:33 Mathieu Olivari wrote: >> This change is done as a follow-up to the following thread: >> https://lkml.org/lkml/2014/10/1/436 >> >> qcom-wdt is currently assuming the presence of a dedicated node in DT >> to gets its configuration. However, on msm architecture, the watchdog is >> usually part of the timer block. So this patch-set is changing the driver >> and slightly enhancing the timer DT bindings to provide the relevant clocks >> and interrupts. >> >> Mathieu Olivari (3): >> watchdog: qcom: use timer devicetree binding >> ARM: qcom: add description of KPSS WDT for IPQ8064 >> ARM: msm: add watchdog entries to DT timer binding doc >> >> Documentation/devicetree/bindings/arm/msm/timer.txt | 16 +++++++++++++--- >> arch/arm/boot/dts/qcom-ipq8064.dtsi | 14 +++++++++++++- >> drivers/watchdog/qcom-wdt.c | 21 +++++++++++++++------ >> 3 files changed, 41 insertions(+), 10 deletions(-) >> >> > What about the binding document in > Documentation/devicetree/bindings/watchdog/qcom-wdt.txt? > > We can rewrite it for platforms starting with msm8974 and beyond or delete it and write a new binding. It's a similar hardware block split out from the timers and then made to use a SPI instead of a PPI for the interrupt sources. We also lost the CPU remapping feature so there is really only one watchdog instead of 2 per cpu. Oh and the register offsets are different, but otherwise the registers are the same. ---8<----- From: Stephen Boyd Subject: [PATCH] Documentation: qcom-wdt: Update binding for individual block On msm8974 and beyond the KPSS watchdog is split out of the timer block and made to be a single instance instead of per-cpu. Let's update the binding to reflect this and replace the binding that is handled by the qcom,kpss-timer binding. Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/watchdog/qcom-wdt.txt | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt index 4726924d034e..78b92bec4c3a 100644 --- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt @@ -2,14 +2,10 @@ Qualcomm Krait Processor Sub-system (KPSS) Watchdog --------------------------------------------------- Required properties : -- compatible : shall contain only one of the following: - - "qcom,kpss-wdt-msm8960" - "qcom,kpss-wdt-apq8064" - "qcom,kpss-wdt-ipq8064" - +- compatible : shall contain "qcom,kpss-wdt" - reg : shall contain base register location and length - clocks : shall contain the input clock +- interrupts : shall contain the bark and bite interrupts in that order Optional properties : - timeout-sec : shall contain the default watchdog timeout in seconds, @@ -17,8 +13,9 @@ Optional properties : Example: watchdog@208a038 { - compatible = "qcom,kpss-wdt-ipq8064"; - reg = <0x0208a038 0x40>; + compatible = "qcom,kpss-wdt"; + reg = <0xf9017000 0x1000>; + interrupts = <0 3 0>, <0 4 0>; clocks = <&sleep_clk>; timeout-sec = <10>; };