| Message ID | 20251027154615.115759-4-biju.das.jz@bp.renesas.com |
|---|---|
| State | New |
| Headers | show |
| Series | None | expand |
On Mon, Oct 27, 2025 at 03:45:50PM +0000, Biju Das wrote: > Add documentation for the serial communication interface (RSCI) found on > the Renesas RZ/G3E (R9A09G047) SoC. The RSCI IP on this SoC is identical > to that on the RZ/T2H (R9A09G077) SoC, but it has a 32-stage FIFO compared > to 16 on RZ/T2H. It supports both FIFO and non-FIFO mode operation. RZ/G3E > has 6 clocks compared to 3 on RZ/T2H, and it has multiple resets. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > .../bindings/serial/renesas,rsci.yaml | 82 ++++++++++++++++--- > 1 file changed, 71 insertions(+), 11 deletions(-) > > diff --git a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml > index 6b1f827a335b..7cf6348e2b5b 100644 > --- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml > +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml > @@ -10,17 +10,16 @@ maintainers: > - Geert Uytterhoeven <geert+renesas@glider.be> > - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > -allOf: > - - $ref: serial.yaml# > - > properties: > compatible: > oneOf: > - - items: > - - const: renesas,r9a09g087-rsci # RZ/N2H > - - const: renesas,r9a09g077-rsci # RZ/T2H > + - enum: > + - renesas,r9a09g047-rsci # RZ/G3E non FIFO mode > + - renesas,r9a09g047-rscif # RZ/G3E FIFO mode > + - renesas,r9a09g077-rsci # RZ/T2H > > - items: > + - const: renesas,r9a09g087-rsci # RZ/N2H > - const: renesas,r9a09g077-rsci # RZ/T2H > > reg: > @@ -42,14 +41,40 @@ properties: > > clocks: > minItems: 2 > - maxItems: 3 > + maxItems: 6 > > clock-names: > - minItems: 2 > + oneOf: > + - items: > + - const: operation > + - const: bus > + - items: > + - const: operation > + - const: bus > + - const: sck # optional external clock input > + - items: > + - const: bus > + - const: tclk > + - const: tclk_div64 > + - const: tclk_div16 > + - const: tclk_div4 > + - items: > + - const: bus > + - const: tclk > + - const: tclk_div64 > + - const: tclk_div16 > + - const: tclk_div4 > + - const: sck # optional external clock input > + > + resets: > + items: > + - description: Input for resetting the APB clock > + - description: Input for resetting TCLK > + > + reset-names: > items: > - - const: operation > - - const: bus > - - const: sck # optional external clock input > + - const: presetn > + - const: tresetn > > power-domains: > maxItems: 1 > @@ -62,6 +87,41 @@ required: > - clock-names > - power-domains > > +allOf: > + - $ref: serial.yaml# > + > + - if: > + properties: > + compatible: > + contains: > + const: renesas,r9a09g077-rsci > + then: > + properties: > + clocks: > + maxItems: 3 > + > + clock-names: > + maxItems: 3 > + > + - if: > + properties: > + compatible: > + contains: > + enum: > + - renesas,r9a09g047-rsci > + - renesas,r9a09g047-rscif > + then: > + properties: > + clocks: > + minItems: 5 > + > + clock-names: > + minItems: 5 > + > + required: > + - resets > + - reset-names Does this need an "else: properties: resets: false"? Or do other devices actually have resets too? > + > unevaluatedProperties: false > > examples: > -- > 2.43.0 >
Hi Conor Dooley, Thanks for the feedback. > -----Original Message----- > From: Conor Dooley <conor@kernel.org> > Sent: 28 October 2025 19:31 > Subject: Re: [PATCH 03/19] dt-bindings: serial: renesas,rsci: Document RZ/G3E support > > On Mon, Oct 27, 2025 at 03:45:50PM +0000, Biju Das wrote: > > Add documentation for the serial communication interface (RSCI) found > > on the Renesas RZ/G3E (R9A09G047) SoC. The RSCI IP on this SoC is > > identical to that on the RZ/T2H (R9A09G077) SoC, but it has a 32-stage > > FIFO compared to 16 on RZ/T2H. It supports both FIFO and non-FIFO mode > > operation. RZ/G3E has 6 clocks compared to 3 on RZ/T2H, and it has multiple resets. > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > --- > > .../bindings/serial/renesas,rsci.yaml | 82 ++++++++++++++++--- > > 1 file changed, 71 insertions(+), 11 deletions(-) > > > > diff --git > > a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml > > b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml > > index 6b1f827a335b..7cf6348e2b5b 100644 > > --- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml > > +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml > > @@ -10,17 +10,16 @@ maintainers: > > - Geert Uytterhoeven <geert+renesas@glider.be> > > - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > -allOf: > > - - $ref: serial.yaml# > > - > > properties: > > compatible: > > oneOf: > > - - items: > > - - const: renesas,r9a09g087-rsci # RZ/N2H > > - - const: renesas,r9a09g077-rsci # RZ/T2H > > + - enum: > > + - renesas,r9a09g047-rsci # RZ/G3E non FIFO mode > > + - renesas,r9a09g047-rscif # RZ/G3E FIFO mode > > + - renesas,r9a09g077-rsci # RZ/T2H > > > > - items: > > + - const: renesas,r9a09g087-rsci # RZ/N2H > > - const: renesas,r9a09g077-rsci # RZ/T2H > > > > reg: > > @@ -42,14 +41,40 @@ properties: > > > > clocks: > > minItems: 2 > > - maxItems: 3 > > + maxItems: 6 > > > > clock-names: > > - minItems: 2 > > + oneOf: > > + - items: > > + - const: operation > > + - const: bus > > + - items: > > + - const: operation > > + - const: bus > > + - const: sck # optional external clock input > > + - items: > > + - const: bus > > + - const: tclk > > + - const: tclk_div64 > > + - const: tclk_div16 > > + - const: tclk_div4 > > + - items: > > + - const: bus > > + - const: tclk > > + - const: tclk_div64 > > + - const: tclk_div16 > > + - const: tclk_div4 > > + - const: sck # optional external clock input > > + > > + resets: > > + items: > > + - description: Input for resetting the APB clock > > + - description: Input for resetting TCLK > > + > > + reset-names: > > items: > > - - const: operation > > - - const: bus > > - - const: sck # optional external clock input > > + - const: presetn > > + - const: tresetn > > > > power-domains: > > maxItems: 1 > > @@ -62,6 +87,41 @@ required: > > - clock-names > > - power-domains > > > > +allOf: > > + - $ref: serial.yaml# > > + > > + - if: > > + properties: > > + compatible: > > + contains: > > + const: renesas,r9a09g077-rsci > > + then: > > + properties: > > + clocks: > > + maxItems: 3 > > + > > + clock-names: > > + maxItems: 3 > > + > > + - if: > > + properties: > > + compatible: > > + contains: > > + enum: > > + - renesas,r9a09g047-rsci > > + - renesas,r9a09g047-rscif > > + then: > > + properties: > > + clocks: > > + minItems: 5 > > + > > + clock-names: > > + minItems: 5 > > + > > + required: > > + - resets > > + - reset-names > > Does this need an "else: properties: resets: false"? Or do other devices actually have resets too? It is not required as resets are optional for RZ/T2H and RZ/N2H. RZ/T2H and N2H does not have Resets. Cheers, Biju > > > + > > unevaluatedProperties: false > > > > examples: > > -- > > 2.43.0 > >
On Tue, Oct 28, 2025 at 07:41:33PM +0000, Biju Das wrote: > > > + - if: > > > + properties: > > > + compatible: > > > + contains: > > > + enum: > > > + - renesas,r9a09g047-rsci > > > + - renesas,r9a09g047-rscif > > > + then: > > > + properties: > > > + clocks: > > > + minItems: 5 > > > + > > > + clock-names: > > > + minItems: 5 > > > + > > > + required: > > > + - resets > > > + - reset-names > > > > Does this need an "else: properties: resets: false"? Or do other devices actually have resets too? > > It is not required as resets are optional for RZ/T2H and RZ/N2H. RZ/T2H and N2H does not have > Resets. This is a contradiction. Either they are optional for these platforms or the platforms do not have resets. Cannot be both!
Hi Conor Dooley, Thanks for the feedback. > -----Original Message----- > From: Conor Dooley <conor@kernel.org> > Sent: 28 October 2025 19:52 > Subject: Re: [PATCH 03/19] dt-bindings: serial: renesas,rsci: Document RZ/G3E support > > On Tue, Oct 28, 2025 at 07:41:33PM +0000, Biju Das wrote: > > > > + - if: > > > > + properties: > > > > + compatible: > > > > + contains: > > > > + enum: > > > > + - renesas,r9a09g047-rsci > > > > + - renesas,r9a09g047-rscif > > > > + then: > > > > + properties: > > > > + clocks: > > > > + minItems: 5 > > > > + > > > > + clock-names: > > > > + minItems: 5 > > > > + > > > > + required: > > > > + - resets > > > > + - reset-names > > > > > > Does this need an "else: properties: resets: false"? Or do other devices actually have resets too? > > > > It is not required as resets are optional for RZ/T2H and RZ/N2H. > > RZ/T2H and N2H does not have Resets. > > This is a contradiction. Either they are optional for these platforms or the platforms do not have > resets. Cannot be both! Some RSCI IP SoCs has resets and some does not have. From RSCI IP point of view this property is optional. I just try to avoid complex if else statements in dt schema by adding Per SoC properties. If you prefer else statements for resets, I can add that as well. Please let me know. Cheers, Biju
On Tue, Oct 28, 2025 at 08:26:08PM +0000, Biju Das wrote: > Hi Conor Dooley, > > Thanks for the feedback. > > > -----Original Message----- > > From: Conor Dooley <conor@kernel.org> > > Sent: 28 October 2025 19:52 > > Subject: Re: [PATCH 03/19] dt-bindings: serial: renesas,rsci: Document RZ/G3E support > > > > On Tue, Oct 28, 2025 at 07:41:33PM +0000, Biju Das wrote: > > > > > + - if: > > > > > + properties: > > > > > + compatible: > > > > > + contains: > > > > > + enum: > > > > > + - renesas,r9a09g047-rsci > > > > > + - renesas,r9a09g047-rscif > > > > > + then: > > > > > + properties: > > > > > + clocks: > > > > > + minItems: 5 > > > > > + > > > > > + clock-names: > > > > > + minItems: 5 > > > > > + > > > > > + required: > > > > > + - resets > > > > > + - reset-names > > > > > > > > Does this need an "else: properties: resets: false"? Or do other devices actually have resets too? > > > > > > It is not required as resets are optional for RZ/T2H and RZ/N2H. > > > RZ/T2H and N2H does not have Resets. > > > > This is a contradiction. Either they are optional for these platforms or the platforms do not have > > resets. Cannot be both! > > Some RSCI IP SoCs has resets and some does not have. From RSCI IP point of view > this property is optional. > > I just try to avoid complex if else statements in dt schema by adding > Per SoC properties. > > If you prefer else statements for resets, I can add that as well. Please let me know. I would prefer that you do that, yes.
diff --git a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml index 6b1f827a335b..7cf6348e2b5b 100644 --- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml @@ -10,17 +10,16 @@ maintainers: - Geert Uytterhoeven <geert+renesas@glider.be> - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> -allOf: - - $ref: serial.yaml# - properties: compatible: oneOf: - - items: - - const: renesas,r9a09g087-rsci # RZ/N2H - - const: renesas,r9a09g077-rsci # RZ/T2H + - enum: + - renesas,r9a09g047-rsci # RZ/G3E non FIFO mode + - renesas,r9a09g047-rscif # RZ/G3E FIFO mode + - renesas,r9a09g077-rsci # RZ/T2H - items: + - const: renesas,r9a09g087-rsci # RZ/N2H - const: renesas,r9a09g077-rsci # RZ/T2H reg: @@ -42,14 +41,40 @@ properties: clocks: minItems: 2 - maxItems: 3 + maxItems: 6 clock-names: - minItems: 2 + oneOf: + - items: + - const: operation + - const: bus + - items: + - const: operation + - const: bus + - const: sck # optional external clock input + - items: + - const: bus + - const: tclk + - const: tclk_div64 + - const: tclk_div16 + - const: tclk_div4 + - items: + - const: bus + - const: tclk + - const: tclk_div64 + - const: tclk_div16 + - const: tclk_div4 + - const: sck # optional external clock input + + resets: + items: + - description: Input for resetting the APB clock + - description: Input for resetting TCLK + + reset-names: items: - - const: operation - - const: bus - - const: sck # optional external clock input + - const: presetn + - const: tresetn power-domains: maxItems: 1 @@ -62,6 +87,41 @@ required: - clock-names - power-domains +allOf: + - $ref: serial.yaml# + + - if: + properties: + compatible: + contains: + const: renesas,r9a09g077-rsci + then: + properties: + clocks: + maxItems: 3 + + clock-names: + maxItems: 3 + + - if: + properties: + compatible: + contains: + enum: + - renesas,r9a09g047-rsci + - renesas,r9a09g047-rscif + then: + properties: + clocks: + minItems: 5 + + clock-names: + minItems: 5 + + required: + - resets + - reset-names + unevaluatedProperties: false examples:
Add documentation for the serial communication interface (RSCI) found on the Renesas RZ/G3E (R9A09G047) SoC. The RSCI IP on this SoC is identical to that on the RZ/T2H (R9A09G077) SoC, but it has a 32-stage FIFO compared to 16 on RZ/T2H. It supports both FIFO and non-FIFO mode operation. RZ/G3E has 6 clocks compared to 3 on RZ/T2H, and it has multiple resets. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- .../bindings/serial/renesas,rsci.yaml | 82 ++++++++++++++++--- 1 file changed, 71 insertions(+), 11 deletions(-)