| Message ID | 20250519160448.209461-3-18255117159@163.com |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | Relax max-link-speed check to support PCIe Gen5/Gen6 | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dt-meta-schema | success |
On Tue, 20 May 2025 00:04:47 +0800, Hans Zhang wrote: > Update the PCI Endpoint (EP) device tree binding documentation to > include PCIe Gen5 and Gen6 support for the `max-link-speed` property. > Similar to the Host Controller binding, the original EP binding > limited this value to 1~4 (Gen1~Gen4). With current SOCs requiring > Gen5/Gen6 support (e.g., Synopsys/Cadence IP), this change aligns > the EP binding with the kernel's PCIe 6.0 capabilities. > > Signed-off-by: Hans Zhang <18255117159@163.com> > --- > Documentation/devicetree/bindings/pci/pci-ep.yaml | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Acked-by: Rob Herring (Arm) <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/pci/pci-ep.yaml b/Documentation/devicetree/bindings/pci/pci-ep.yaml index f75000e3093d..68aaad70b112 100644 --- a/Documentation/devicetree/bindings/pci/pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/pci-ep.yaml @@ -33,7 +33,7 @@ properties: max-link-speed: $ref: /schemas/types.yaml#/definitions/uint32 - enum: [ 1, 2, 3, 4 ] + enum: [ 1, 2, 3, 4, 5, 6] num-lanes: description: maximum number of lanes
Update the PCI Endpoint (EP) device tree binding documentation to include PCIe Gen5 and Gen6 support for the `max-link-speed` property. Similar to the Host Controller binding, the original EP binding limited this value to 1~4 (Gen1~Gen4). With current SOCs requiring Gen5/Gen6 support (e.g., Synopsys/Cadence IP), this change aligns the EP binding with the kernel's PCIe 6.0 capabilities. Signed-off-by: Hans Zhang <18255117159@163.com> --- Documentation/devicetree/bindings/pci/pci-ep.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)