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However TBU is in the path between eDMA3 and ACP, need to bypass the default SID 0 to make eDMA3 work properly. Introduce the property "nxp,imx95-bypass-sid-zero" for bypassing SID 0. Signed-off-by: Peng Fan --- Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml index 75fcf4cb52d9f6449238578f20288966af35cab3..88ab908154e31aabf98f3bbe4df348956f49d5e1 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml @@ -69,6 +69,10 @@ properties: register access with page 0 offsets. Set for Cavium ThunderX2 silicon that doesn't support SMMU page1 register space. + nxp,imx95-bypass-sid-zero: + type: boolean + description: StreamID 0 that needs transaction set as bypass mode. + required: - compatible - reg