| Message ID | 20240930095449.1813195-8-pierre-henry.moussay@microchip.com |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | [linux,v2,01/20] dt-bindings: can: mpfs: add PIC64GX CAN compatibility | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On Mon, Sep 30, 2024 at 10:54:36AM +0100, pierre-henry.moussay@microchip.com wrote: > From: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com> > > PIC64GX SoC Clock Conditioning Circuitry is compatibles > with the Polarfire SoC > > Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com> > --- > .../devicetree/bindings/clock/microchip,mpfs-ccc.yaml | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml > index f1770360798f..9a6b50527c42 100644 > --- a/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml > +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml > @@ -17,7 +17,11 @@ description: | > > properties: > compatible: > - const: microchip,mpfs-ccc > + oneOf: > + - items: > + - const: microchip,pic64gx-ccc > + - const: microchip,mpfs-ccc > + - const: microchip,mpfs-ccc Acked-by: Conor Dooley <conor.dooley@microchip.com> > > reg: > items: > -- > 2.30.2 > >
diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml index f1770360798f..9a6b50527c42 100644 --- a/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml @@ -17,7 +17,11 @@ description: | properties: compatible: - const: microchip,mpfs-ccc + oneOf: + - items: + - const: microchip,pic64gx-ccc + - const: microchip,mpfs-ccc + - const: microchip,mpfs-ccc reg: items: