| Message ID | 20240106215146.147922-1-aford173@gmail.com |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | [V7,1/2] dt-bindings: display: imx: add binding for i.MX8MP HDMI PVI | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
Hi Adam, thanks for pushing this forward. Am Samstag, 6. Januar 2024, 22:51:45 CET schrieb Adam Ford: > From: Lucas Stach <l.stach@pengutronix.de> > > This IP block is found in the HDMI subsystem of the i.MX8MP SoC. It has a > full timing generator and can switch between different video sources. On > the i.MX8MP however the only supported source is the LCDIF. The block > just needs to be powered up and told about the polarity of the video > sync signals to act in bypass mode. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> (v2) > Tested-by: Marek Vasut <marex@denx.de> (v1) > Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> (v2) > Tested-by: Richard Leitner <richard.leitner@skidata.com> (v2) > Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> (v2) > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> (v3) > Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> > Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> > Tested-by: Fabio Estevam <festevam@gmail.com> > Signed-off-by: Adam Ford <aford173@gmail.com> Tested on TQMa8MPQL/MBa8MPxL + Full-HD HDMI monitor. Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> > > --- > V7: Re-do some includes to address build issues after rebasing from > Linux-next > > V6: No change. > > V5: I (Adam) tried to help move this along, so I took Lucas' patch and > attempted to apply fixes based on feedback. I don't have > all the history, so apologies for that. > No changes from V4 to V5 > > diff --git a/drivers/gpu/drm/bridge/imx/Kconfig > b/drivers/gpu/drm/bridge/imx/Kconfig index 5a4f3d58501e..a4d13331e320 > 100644 > --- a/drivers/gpu/drm/bridge/imx/Kconfig > +++ b/drivers/gpu/drm/bridge/imx/Kconfig > @@ -3,6 +3,13 @@ if ARCH_MXC || COMPILE_TEST > config DRM_IMX_LDB_HELPER > tristate > > +config DRM_IMX8MP_HDMI_PVI > + tristate "Freescale i.MX8MP HDMI PVI bridge support" > + depends on OF > + help > + Choose this to enable support for the internal HDMI TX Parallel > + Video Interface found on the Freescale i.MX8MP SoC. > + > config DRM_IMX8QM_LDB > tristate "Freescale i.MX8QM LVDS display bridge" > depends on OF > diff --git a/drivers/gpu/drm/bridge/imx/Makefile > b/drivers/gpu/drm/bridge/imx/Makefile index 2b0c2e44aa1b..e2c2106509fa > 100644 > --- a/drivers/gpu/drm/bridge/imx/Makefile > +++ b/drivers/gpu/drm/bridge/imx/Makefile > @@ -1,4 +1,5 @@ > obj-$(CONFIG_DRM_IMX_LDB_HELPER) += imx-ldb-helper.o > +obj-$(CONFIG_DRM_IMX8MP_HDMI_PVI) += imx8mp-hdmi-pvi.o > obj-$(CONFIG_DRM_IMX8QM_LDB) += imx8qm-ldb.o > obj-$(CONFIG_DRM_IMX8QXP_LDB) += imx8qxp-ldb.o > obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o > diff --git a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c > b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c new file mode 100644 > index 000000000000..a76b7669fe8a > --- /dev/null > +++ b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c > @@ -0,0 +1,207 @@ > +// SPDX-License-Identifier: GPL-2.0+ > + > +/* > + * Copyright (C) 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de> > + */ > + > +#include <drm/drm_atomic_helper.h> > +#include <drm/drm_bridge.h> > +#include <drm/drm_crtc.h> > +#include <linux/bitfield.h> > +#include <linux/io.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_graph.h> > +#include <linux/platform_device.h> > +#include <linux/pm_runtime.h> > + > +#define HTX_PVI_CTRL 0x0 > +#define PVI_CTRL_OP_VSYNC_POL BIT(18) > +#define PVI_CTRL_OP_HSYNC_POL BIT(17) > +#define PVI_CTRL_OP_DE_POL BIT(16) > +#define PVI_CTRL_INP_VSYNC_POL BIT(14) > +#define PVI_CTRL_INP_HSYNC_POL BIT(13) > +#define PVI_CTRL_INP_DE_POL BIT(12) > +#define PVI_CTRL_MODE_MASK GENMASK(2, 1) > +#define PVI_CTRL_MODE_LCDIF 2 > +#define PVI_CTRL_EN BIT(0) > + > +struct imx8mp_hdmi_pvi { > + struct drm_bridge bridge; > + struct device *dev; > + struct drm_bridge *next_bridge; > + void __iomem *regs; > +}; > + > +static inline struct imx8mp_hdmi_pvi * > +to_imx8mp_hdmi_pvi(struct drm_bridge *bridge) > +{ > + return container_of(bridge, struct imx8mp_hdmi_pvi, bridge); > +} > + > +static int imx8mp_hdmi_pvi_bridge_attach(struct drm_bridge *bridge, > + enum drm_bridge_attach_flags flags) > +{ > + struct imx8mp_hdmi_pvi *pvi = to_imx8mp_hdmi_pvi(bridge); > + > + return drm_bridge_attach(bridge->encoder, pvi->next_bridge, > + bridge, flags); > +} > + > +static void imx8mp_hdmi_pvi_bridge_enable(struct drm_bridge *bridge, > + struct drm_bridge_state *bridge_state) > +{ > + struct drm_atomic_state *state = bridge_state->base.state; > + struct imx8mp_hdmi_pvi *pvi = to_imx8mp_hdmi_pvi(bridge); > + struct drm_connector_state *conn_state; > + const struct drm_display_mode *mode; > + struct drm_crtc_state *crtc_state; > + struct drm_connector *connector; > + u32 bus_flags, val; > + > + connector = drm_atomic_get_new_connector_for_encoder(state, > bridge->encoder); + conn_state = drm_atomic_get_new_connector_state(state, > connector); + crtc_state = drm_atomic_get_new_crtc_state(state, > conn_state->crtc); + > + if (WARN_ON(pm_runtime_resume_and_get(pvi->dev))) > + return; > + > + mode = &crtc_state->adjusted_mode; > + > + val = FIELD_PREP(PVI_CTRL_MODE_MASK, PVI_CTRL_MODE_LCDIF) | PVI_CTRL_EN; > + > + if (mode->flags & DRM_MODE_FLAG_PVSYNC) > + val |= PVI_CTRL_OP_VSYNC_POL | PVI_CTRL_INP_VSYNC_POL; > + > + if (mode->flags & DRM_MODE_FLAG_PHSYNC) > + val |= PVI_CTRL_OP_HSYNC_POL | PVI_CTRL_INP_HSYNC_POL; > + > + if (pvi->next_bridge->timings) > + bus_flags = pvi->next_bridge->timings->input_bus_flags; > + else if (bridge_state) > + bus_flags = bridge_state->input_bus_cfg.flags; > + > + if (bus_flags & DRM_BUS_FLAG_DE_HIGH) > + val |= PVI_CTRL_OP_DE_POL | PVI_CTRL_INP_DE_POL; > + > + writel(val, pvi->regs + HTX_PVI_CTRL); > +} > + > +static void imx8mp_hdmi_pvi_bridge_disable(struct drm_bridge *bridge, > + struct drm_bridge_state *bridge_state) > +{ > + struct imx8mp_hdmi_pvi *pvi = to_imx8mp_hdmi_pvi(bridge); > + > + writel(0x0, pvi->regs + HTX_PVI_CTRL); > + > + pm_runtime_put(pvi->dev); > +} > + > +static u32 * > +imx8mp_hdmi_pvi_bridge_get_input_bus_fmts(struct drm_bridge *bridge, > + struct drm_bridge_state *bridge_state, > + struct drm_crtc_state *crtc_state, > + struct drm_connector_state *conn_state, > + u32 output_fmt, > + unsigned int *num_input_fmts) > +{ > + struct imx8mp_hdmi_pvi *pvi = to_imx8mp_hdmi_pvi(bridge); > + struct drm_bridge *next_bridge = pvi->next_bridge; > + struct drm_bridge_state *next_state; > + > + if (!next_bridge->funcs->atomic_get_input_bus_fmts) > + return 0; > + > + next_state = drm_atomic_get_new_bridge_state(crtc_state->state, > + next_bridge); > + > + return next_bridge->funcs->atomic_get_input_bus_fmts(next_bridge, > + next_state, > + crtc_state, > + conn_state, > + output_fmt, > + num_input_fmts); > +} > + > +static const struct drm_bridge_funcs imx_hdmi_pvi_bridge_funcs = { > + .attach = imx8mp_hdmi_pvi_bridge_attach, > + .atomic_enable = imx8mp_hdmi_pvi_bridge_enable, > + .atomic_disable = imx8mp_hdmi_pvi_bridge_disable, > + .atomic_get_input_bus_fmts = imx8mp_hdmi_pvi_bridge_get_input_bus_fmts, > + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, > + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, > + .atomic_reset = drm_atomic_helper_bridge_reset, > +}; > + > +static int imx8mp_hdmi_pvi_probe(struct platform_device *pdev) > +{ > + struct device_node *remote; > + struct imx8mp_hdmi_pvi *pvi; > + > + pvi = devm_kzalloc(&pdev->dev, sizeof(*pvi), GFP_KERNEL); > + if (!pvi) > + return -ENOMEM; > + > + platform_set_drvdata(pdev, pvi); > + pvi->dev = &pdev->dev; > + > + pvi->regs = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(pvi->regs)) > + return PTR_ERR(pvi->regs); > + > + /* Get the next bridge in the pipeline. */ > + remote = of_graph_get_remote_node(pdev->dev.of_node, 1, -1); > + if (!remote) > + return -EINVAL; > + > + pvi->next_bridge = of_drm_find_bridge(remote); > + of_node_put(remote); > + > + if (!pvi->next_bridge) > + return dev_err_probe(&pdev->dev, -EPROBE_DEFER, > + "could not find next bridge\n"); > + > + pm_runtime_enable(&pdev->dev); > + > + /* Register the bridge. */ > + pvi->bridge.funcs = &imx_hdmi_pvi_bridge_funcs; > + pvi->bridge.of_node = pdev->dev.of_node; > + pvi->bridge.timings = pvi->next_bridge->timings; > + > + drm_bridge_add(&pvi->bridge); > + > + return 0; > +} > + > +static int imx8mp_hdmi_pvi_remove(struct platform_device *pdev) > +{ > + struct imx8mp_hdmi_pvi *pvi = platform_get_drvdata(pdev); > + > + drm_bridge_remove(&pvi->bridge); > + > + pm_runtime_disable(&pdev->dev); > + > + return 0; > +} > + > +static const struct of_device_id imx8mp_hdmi_pvi_match[] = { > + { > + .compatible = "fsl,imx8mp-hdmi-pvi", > + }, { > + /* sentinel */ > + } > +}; > +MODULE_DEVICE_TABLE(of, imx8mp_hdmi_pvi_match); > + > +static struct platform_driver imx8mp_hdmi_pvi_driver = { > + .probe = imx8mp_hdmi_pvi_probe, > + .remove = imx8mp_hdmi_pvi_remove, > + .driver = { > + .name = "imx-hdmi-pvi", > + .of_match_table = imx8mp_hdmi_pvi_match, > + }, > +}; > +module_platform_driver(imx8mp_hdmi_pvi_driver); > + > +MODULE_DESCRIPTION("i.MX8MP HDMI TX Parallel Video Interface bridge > driver"); +MODULE_LICENSE("GPL");
Hi Adam, thanks for pushing this forward. Am Samstag, 6. Januar 2024, 22:51:44 CET schrieb Adam Ford: > From: Lucas Stach <l.stach@pengutronix.de> > > Add binding for the i.MX8MP HDMI parallel video interface block. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > Signed-off-by: Adam Ford <aford173@gmail.com> > --- > V7: No Change > > V6: Add s-o-b message for myself (Adam) > > V5: I tried to help move this along, so I took Lucas' patch and > attempted to apply fixes based on feedback. I don't have > all the history, so apologies for that. > Removed the pipe character from the Description. > Increased the register size from 0x40 to 0x44. > diff --git > a/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml > b/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml > new file mode 100644 > index 000000000000..3377f152f319 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml > @@ -0,0 +1,83 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/imx/fsl,imx8mp-hdmi-pvi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Freescale i.MX8MP HDMI Parallel Video Interface > + > +maintainers: > + - Lucas Stach <l.stach@pengutronix.de> > + > +description: > + The HDMI parallel video interface is a timing and sync generator block in > the + i.MX8MP SoC, that sits between the video source and the HDMI TX > controller. + > +properties: > + compatible: > + const: fsl,imx8mp-hdmi-pvi > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: Input from the LCDIF controller. > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: Output to the HDMI TX controller. > + > + required: > + - port@0 > + - port@1 > + > +required: > + - compatible > + - reg > + - interrupts > + - power-domains > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/power/imx8mp-power.h> > + > + display-bridge@32fc4000 { > + compatible = "fsl,imx8mp-hdmi-pvi"; > + reg = <0x32fc4000 0x44>; Shall interrupt-parent = <&irqsteer_hdmi>; be added here as well? Best regards, Alexander > + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; > + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + pvi_from_lcdif3: endpoint { > + remote-endpoint = <&lcdif3_to_pvi>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + pvi_to_hdmi_tx: endpoint { > + remote-endpoint = <&hdmi_tx_from_pvi>; > + }; > + }; > + }; > + };
On Wed, Jan 10, 2024 at 5:48 AM Alexander Stein <alexander.stein@ew.tq-group.com> wrote: > > Hi Adam, > > thanks for pushing this forward. > > Am Samstag, 6. Januar 2024, 22:51:44 CET schrieb Adam Ford: > > From: Lucas Stach <l.stach@pengutronix.de> > > > > Add binding for the i.MX8MP HDMI parallel video interface block. > > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > Signed-off-by: Adam Ford <aford173@gmail.com> > > --- > > V7: No Change > > > > V6: Add s-o-b message for myself (Adam) > > > > V5: I tried to help move this along, so I took Lucas' patch and > > attempted to apply fixes based on feedback. I don't have > > all the history, so apologies for that. > > Removed the pipe character from the Description. > > Increased the register size from 0x40 to 0x44. > > diff --git > > a/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml > > b/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml > > new file mode 100644 > > index 000000000000..3377f152f319 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml > > @@ -0,0 +1,83 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/display/imx/fsl,imx8mp-hdmi-pvi.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Freescale i.MX8MP HDMI Parallel Video Interface > > + > > +maintainers: > > + - Lucas Stach <l.stach@pengutronix.de> > > + > > +description: > > + The HDMI parallel video interface is a timing and sync generator block in > > the + i.MX8MP SoC, that sits between the video source and the HDMI TX > > controller. + > > +properties: > > + compatible: > > + const: fsl,imx8mp-hdmi-pvi > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 1 > > + > > + power-domains: > > + maxItems: 1 > > + > > + ports: > > + $ref: /schemas/graph.yaml#/properties/ports > > + > > + properties: > > + port@0: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: Input from the LCDIF controller. > > + > > + port@1: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: Output to the HDMI TX controller. > > + > > + required: > > + - port@0 > > + - port@1 > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + - power-domains > > + - ports > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/irq.h> > > + #include <dt-bindings/power/imx8mp-power.h> > > + > > + display-bridge@32fc4000 { > > + compatible = "fsl,imx8mp-hdmi-pvi"; > > + reg = <0x32fc4000 0x44>; > > Shall interrupt-parent = <&irqsteer_hdmi>; be added here as well? That does appear to the case. Good catch. The HDMI documentation isn't as thorough as some other parts of the tech ref manual are. I'll fix this when I resubmit adam > > Best regards, > Alexander > > > + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; > > + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + port@0 { > > + reg = <0>; > > + pvi_from_lcdif3: endpoint { > > + remote-endpoint = <&lcdif3_to_pvi>; > > + }; > > + }; > > + > > + port@1 { > > + reg = <1>; > > + pvi_to_hdmi_tx: endpoint { > > + remote-endpoint = <&hdmi_tx_from_pvi>; > > + }; > > + }; > > + }; > > + }; > > > -- > TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany > Amtsgericht München, HRB 105018 > Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider > http://www.tq-group.com/ > >
On Sat, 6 Jan 2024 15:51:45 -0600 Adam Ford <aford173@gmail.com> wrote: > From: Lucas Stach <l.stach@pengutronix.de> > > This IP block is found in the HDMI subsystem of the i.MX8MP SoC. It has a > full timing generator and can switch between different video sources. On > the i.MX8MP however the only supported source is the LCDIF. The block > just needs to be powered up and told about the polarity of the video > sync signals to act in bypass mode. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> (v2) > Tested-by: Marek Vasut <marex@denx.de> (v1) > Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> (v2) > Tested-by: Richard Leitner <richard.leitner@skidata.com> (v2) > Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> (v2) > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> (v3) > Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> > Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> > Tested-by: Fabio Estevam <festevam@gmail.com> > Signed-off-by: Adam Ford <aford173@gmail.com> On v6.8-rc1, custom hardware based on the Avnet i.MX8MP SMARC SoM. Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> I think you can remove the Tested-by I sent for previous versions. Luca
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml new file mode 100644 index 000000000000..3377f152f319 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx8mp-hdmi-pvi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8MP HDMI Parallel Video Interface + +maintainers: + - Lucas Stach <l.stach@pengutronix.de> + +description: + The HDMI parallel video interface is a timing and sync generator block in the + i.MX8MP SoC, that sits between the video source and the HDMI TX controller. + +properties: + compatible: + const: fsl,imx8mp-hdmi-pvi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input from the LCDIF controller. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Output to the HDMI TX controller. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - interrupts + - power-domains + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/imx8mp-power.h> + + display-bridge@32fc4000 { + compatible = "fsl,imx8mp-hdmi-pvi"; + reg = <0x32fc4000 0x44>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + pvi_from_lcdif3: endpoint { + remote-endpoint = <&lcdif3_to_pvi>; + }; + }; + + port@1 { + reg = <1>; + pvi_to_hdmi_tx: endpoint { + remote-endpoint = <&hdmi_tx_from_pvi>; + }; + }; + }; + };