diff mbox series

[v6,02/11] dt-bindings: arm: fsl: add imx-se-fw binding doc

Message ID 20230927175401.1962733-3-pankaj.gupta@nxp.com
State Changes Requested
Headers show
Series firmware: imx: NXP Secure-Enclave FW Driver | expand

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Commit Message

Pankaj Gupta Sept. 27, 2023, 5:53 p.m. UTC
The NXP's i.MX EdgeLock Enclave, a HW IP creating an embedded
secure enclave within the SoC boundary to enable features like
- HSM
- SHE
- V2X

Communicates via message unit with linux kernel. This driver
is enables communication ensuring well defined message sequence
protocol between Application Core and enclave's firmware.

Driver configures multiple misc-device on the MU, for multiple
user-space applications can communicate on single MU.

It exists on some i.MX processors. e.g. i.MX8ULP, i.MX93 etc.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
---
 .../bindings/firmware/fsl,imx-se-fw.yaml      | 73 +++++++++++++++++++
 1 file changed, 73 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/firmware/fsl,imx-se-fw.yaml

Comments

Rob Herring (Arm) Sept. 28, 2023, 6:51 p.m. UTC | #1
On Wed, Sep 27, 2023 at 11:23:52PM +0530, Pankaj Gupta wrote:
> The NXP's i.MX EdgeLock Enclave, a HW IP creating an embedded
> secure enclave within the SoC boundary to enable features like
> - HSM
> - SHE
> - V2X
> 
> Communicates via message unit with linux kernel. This driver
> is enables communication ensuring well defined message sequence
> protocol between Application Core and enclave's firmware.
> 
> Driver configures multiple misc-device on the MU, for multiple
> user-space applications can communicate on single MU.
> 
> It exists on some i.MX processors. e.g. i.MX8ULP, i.MX93 etc.
> 
> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
> ---
>  .../bindings/firmware/fsl,imx-se-fw.yaml      | 73 +++++++++++++++++++
>  1 file changed, 73 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/firmware/fsl,imx-se-fw.yaml
> 
> diff --git a/Documentation/devicetree/bindings/firmware/fsl,imx-se-fw.yaml b/Documentation/devicetree/bindings/firmware/fsl,imx-se-fw.yaml
> new file mode 100644
> index 000000000000..d250794432b3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/firmware/fsl,imx-se-fw.yaml
> @@ -0,0 +1,73 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/firmware/fsl,imx-se-fw.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP i.MX EdgeLock Enclave Firmware (ELEFW)
> +
> +maintainers:
> +  - Pankaj Gupta <pankaj.gupta@nxp.com>
> +
> +description:

Need '|' to preserve formatting.

> +  The NXP's i.MX EdgeLock Enclave, a HW IP creating an embedded
> +  secure enclave within the SoC boundary to enable features like
> +  - HSM
> +  - SHE
> +  - V2X
> +
> +  It uses message unit to communicate and coordinate to pass messages
> +  (e.g., data,  status and control) through its interfaces.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - fsl,imx8ulp-se-fw
> +      - fsl,imx93-se-fw

The firmware is not compatible across chips?

> +
> +  mboxes:
> +    description:
> +      All MU channels must be within the same MU instance. Cross instances are
> +      not allowed. Users need to ensure that used MU instance does not conflict
> +      with other execution environments.
> +    items:
> +      - description: TX0 MU channel
> +      - description: RX0 MU channel
> +
> +  mbox-names:
> +    items:
> +      - const: tx
> +      - const: rx
> +
> +  fsl,mu-id:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      Identifier to the message-unit among the multiple message-unit that exists on SoC.
> +      Per message-unit, multiple misc-devices are created, that are  used by userspace

Extra space in there.

Wrap lines at 80 unless there's a benefit to going to 100.

> +      application as logical-waiter and logical-receiver.
> +
> +  memory-region:
> +    items:
> +      - description: Reserved memory region that can be accessed by firmware. Used for
> +          exchanging the buffers between driver and firmware.
> +
> +  fsl,sram:

Just the common 'sram' property.

> +    description: Phandle to the device SRAM

Used for what?

> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +
> +required:
> +  - compatible
> +  - mboxes
> +  - mbox-names
> +  - fsl,mu-id

How is memory-region optional?

> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    ele_fw: se-fw {

Drop unused labels.

> +      compatible = "fsl,imx8ulp-se-fw";
> +      mbox-names = "tx", "rx";
> +      mboxes = <&s4muap 0 0>, <&s4muap 1 0>;
> +      fsl,mu-id = <2>;
> +    };
> -- 
> 2.34.1
>
Pankaj Gupta Oct. 4, 2023, 4:10 a.m. UTC | #2
> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Friday, September 29, 2023 12:22 AM
> To: Pankaj Gupta <pankaj.gupta@nxp.com>
> Cc: shawnguo@kernel.org; s.hauer@pengutronix.de;
> kernel@pengutronix.de; clin@suse.com; conor+dt@kernel.org;
> pierre.gondois@arm.com; festevam@gmail.com; dl-linux-imx <linux-
> imx@nxp.com>; davem@davemloft.net; krzysztof.kozlowski+dt@linaro.org;
> linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; Gaurav Jain <gaurav.jain@nxp.com>;
> alexander.stein@ew.tq-group.com; Varun Sethi <V.Sethi@nxp.com>
> Subject: [EXT] Re: [PATCH v6 02/11] dt-bindings: arm: fsl: add imx-se-fw
> binding doc
> 
> Caution: This is an external email. Please take care when clicking links or
> opening attachments. When in doubt, report the message using the 'Report
> this email' button
> 
> 
> On Wed, Sep 27, 2023 at 11:23:52PM +0530, Pankaj Gupta wrote:
> > The NXP's i.MX EdgeLock Enclave, a HW IP creating an embedded secure
> > enclave within the SoC boundary to enable features like
> > - HSM
> > - SHE
> > - V2X
> >
> > Communicates via message unit with linux kernel. This driver is
> > enables communication ensuring well defined message sequence protocol
> > between Application Core and enclave's firmware.
> >
> > Driver configures multiple misc-device on the MU, for multiple
> > user-space applications can communicate on single MU.
> >
> > It exists on some i.MX processors. e.g. i.MX8ULP, i.MX93 etc.
> >
> > Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
> > ---
> >  .../bindings/firmware/fsl,imx-se-fw.yaml      | 73 +++++++++++++++++++
> >  1 file changed, 73 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/firmware/fsl,imx-se-fw.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/firmware/fsl,imx-se-fw.yaml
> > b/Documentation/devicetree/bindings/firmware/fsl,imx-se-fw.yaml
> > new file mode 100644
> > index 000000000000..d250794432b3
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/firmware/fsl,imx-se-fw.yaml
> > @@ -0,0 +1,73 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> >
> +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fschemas%2Ffirmware%2Ffsl%2Cimx-se-
> fw.yaml%23&data=05%7C0
> >
> +1%7Cpankaj.gupta%40nxp.com%7C5ec9b97100834814d30608dbc054010a%7
> C686ea
> >
> +1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C638315239256248220%7CUnk
> nown%7C
> >
> +TWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwi
> LCJXV
> >
> +CI6Mn0%3D%7C3000%7C%7C%7C&sdata=5%2BuUxUzFCRHsi17vX83tGcJijp
> HsNAxd5Fu
> > +Ws4qT9Lw%3D&reserved=0
> > +$schema:
> >
> +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fmeta-
> schemas%2Fcore.yaml%23&data=05%7C01%7Cpankaj.gupta%
> >
> +40nxp.com%7C5ec9b97100834814d30608dbc054010a%7C686ea1d3bc2b4c6f
> a92cd9
> >
> +9c5c301635%7C0%7C0%7C638315239256248220%7CUnknown%7CTWFpbGZ
> sb3d8eyJWI
> >
> +joiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7
> C3000%
> >
> +7C%7C%7C&sdata=o1LjAT7gJVTb66L21HyhfY9dGh8uKIFNHWKg%2FLNBMO
> 8%3D&reser
> > +ved=0
> > +
> > +title: NXP i.MX EdgeLock Enclave Firmware (ELEFW)
> > +
> > +maintainers:
> > +  - Pankaj Gupta <pankaj.gupta@nxp.com>
> > +
> > +description:
> 
> Need '|' to preserve formatting.

Accepted.
> 
> > +  The NXP's i.MX EdgeLock Enclave, a HW IP creating an embedded
> > + secure enclave within the SoC boundary to enable features like
> > +  - HSM
> > +  - SHE
> > +  - V2X
> > +
> > +  It uses message unit to communicate and coordinate to pass messages
> > + (e.g., data,  status and control) through its interfaces.
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - fsl,imx8ulp-se-fw
> > +      - fsl,imx93-se-fw
> 
> The firmware is not compatible across chips?
	
The secure-enclave hardware varies from one SoC to another.
Hence, FW varies too, from one SoC, to other.

> 
> > +
> > +  mboxes:
> > +    description:
> > +      All MU channels must be within the same MU instance. Cross instances
> are
> > +      not allowed. Users need to ensure that used MU instance does not
> conflict
> > +      with other execution environments.
> > +    items:
> > +      - description: TX0 MU channel
> > +      - description: RX0 MU channel
> > +
> > +  mbox-names:
> > +    items:
> > +      - const: tx
> > +      - const: rx
> > +
> > +  fsl,mu-id:
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    description:
> > +      Identifier to the message-unit among the multiple message-unit that
> exists on SoC.
> > +      Per message-unit, multiple misc-devices are created, that are
> > + used by userspace
> 
> Extra space in there.

Accepted.
> 
> Wrap lines at 80 unless there's a benefit to going to 100.
> 
Accepted.

> > +      application as logical-waiter and logical-receiver.
> > +
> > +  memory-region:
> > +    items:
> > +      - description: Reserved memory region that can be accessed by
> firmware. Used for
> > +          exchanging the buffers between driver and firmware.
> > +
> > +  fsl,sram:
> 
> Just the common 'sram' property.
Ok

> 
> > +    description: Phandle to the device SRAM
> 
> Used for what?
Accepted and will add the details on the usage.

> 
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +
> > +required:
> > +  - compatible
> > +  - mboxes
> > +  - mbox-names
> > +  - fsl,mu-id
> 
> How is memory-region optional?
Depending on the type of enclave IP and the FW, memory-region is configured optionally.
For i.MX8ULP and i.MX93, it is required. For i.MX8DXL, it is not required.
> 
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    ele_fw: se-fw {
> 
> Drop unused labels.
I am sorry, if I am not able to understand your point here.
But, all the below labels are getting used.
I can remove the fsl,mu-id. Will do it in V7.

> 
> > +      compatible = "fsl,imx8ulp-se-fw";
> > +      mbox-names = "tx", "rx";
> > +      mboxes = <&s4muap 0 0>, <&s4muap 1 0>;
> > +      fsl,mu-id = <2>;
> > +    };
> > --
> > 2.34.1
> >
Krzysztof Kozlowski Oct. 4, 2023, 6:36 a.m. UTC | #3
On 04/10/2023 06:10, Pankaj Gupta wrote:

>>
>>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
>>> +
>>> +required:
>>> +  - compatible
>>> +  - mboxes
>>> +  - mbox-names
>>> +  - fsl,mu-id
>>
>> How is memory-region optional?
> Depending on the type of enclave IP and the FW, memory-region is configured optionally.
> For i.MX8ULP and i.MX93, it is required. For i.MX8DXL, it is not required.

Then write it in the bindings in allOf:if:then:.

>>
>>> +
>>> +additionalProperties: false
>>> +
>>> +examples:
>>> +  - |
>>> +    ele_fw: se-fw {
>>
>> Drop unused labels.
> I am sorry, if I am not able to understand your point here.
> But, all the below labels are getting used.
> I can remove the fsl,mu-id. Will do it in V7.

Comment was about labels, not properties.

Best regards,
Krzysztof
Pankaj Gupta Oct. 26, 2023, 11:23 a.m. UTC | #4
> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Wednesday, October 4, 2023 12:06 PM
> To: Pankaj Gupta <pankaj.gupta@nxp.com>; Rob Herring <robh@kernel.org>
> Cc: shawnguo@kernel.org; s.hauer@pengutronix.de;
> kernel@pengutronix.de; clin@suse.com; conor+dt@kernel.org;
> pierre.gondois@arm.com; festevam@gmail.com; dl-linux-imx <linux-
> imx@nxp.com>; davem@davemloft.net; krzysztof.kozlowski+dt@linaro.org;
> linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; Gaurav Jain <gaurav.jain@nxp.com>;
> alexander.stein@ew.tq-group.com; Varun Sethi <V.Sethi@nxp.com>
> Subject: Re: [EXT] Re: [PATCH v6 02/11] dt-bindings: arm: fsl: add imx-se-fw
> binding doc
> 
> Caution: This is an external email. Please take care when clicking links or
> opening attachments. When in doubt, report the message using the 'Report
> this email' button
> 
> 
> On 04/10/2023 06:10, Pankaj Gupta wrote:
> 
> >>
> >>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> >>> +
> >>> +required:
> >>> +  - compatible
> >>> +  - mboxes
> >>> +  - mbox-names
> >>> +  - fsl,mu-id
> >>
> >> How is memory-region optional?
> > Depending on the type of enclave IP and the FW, memory-region is
> configured optionally.
> > For i.MX8ULP and i.MX93, it is required. For i.MX8DXL, it is not required.
> 
> Then write it in the bindings in allOf:if:then:.
Accepted.

> 
> >>
> >>> +
> >>> +additionalProperties: false
> >>> +
> >>> +examples:
> >>> +  - |
> >>> +    ele_fw: se-fw {
> >>
> >> Drop unused labels.
> > I am sorry, if I am not able to understand your point here.
> > But, all the below labels are getting used.
> > I can remove the fsl,mu-id. Will do it in V7.
> 
> Comment was about labels, not properties.
The label "ele_fw", is needed to be placed in different DTSI file.

For instance, node is added in i.mx93.dtsi.
Using label, the memory-region property dependent on size of DDR on the platform, is placed in:

- imx93-11x11-evk.dts
 

> 
> Best regards,
> Krzysztof
Conor Dooley Oct. 26, 2023, 1:55 p.m. UTC | #5
> > >>> +
> > >>> +additionalProperties: false
> > >>> +
> > >>> +examples:
> > >>> +  - |
> > >>> +    ele_fw: se-fw {
> > >>
> > >> Drop unused labels.
> > > I am sorry, if I am not able to understand your point here.
> > > But, all the below labels are getting used.
> > > I can remove the fsl,mu-id. Will do it in V7.
> > 
> > Comment was about labels, not properties.
> The label "ele_fw", is needed to be placed in different DTSI file.
> 
> For instance, node is added in i.mx93.dtsi.
> Using label, the memory-region property dependent on size of DDR on the platform, is placed in:
> 
> - imx93-11x11-evk.dts

This is a standalone example, whether or not you need a label in the
dts/dtsi is not relevant to this example.
Krzysztof Kozlowski Oct. 27, 2023, 7:08 a.m. UTC | #6
On 26/10/2023 13:23, Pankaj Gupta wrote:
>>>>> +additionalProperties: false
>>>>> +
>>>>> +examples:
>>>>> +  - |
>>>>> +    ele_fw: se-fw {
>>>>
>>>> Drop unused labels.
>>> I am sorry, if I am not able to understand your point here.
>>> But, all the below labels are getting used.
>>> I can remove the fsl,mu-id. Will do it in V7.
>>
>> Comment was about labels, not properties.
> The label "ele_fw", is needed to be placed in different DTSI file.
> 
> For instance, node is added in i.mx93.dtsi.
> Using label, the memory-region property dependent on size of DDR on the platform, is placed in:
> 
> - imx93-11x11-evk.dts

And how is this related to this patch?

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/firmware/fsl,imx-se-fw.yaml b/Documentation/devicetree/bindings/firmware/fsl,imx-se-fw.yaml
new file mode 100644
index 000000000000..d250794432b3
--- /dev/null
+++ b/Documentation/devicetree/bindings/firmware/fsl,imx-se-fw.yaml
@@ -0,0 +1,73 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/firmware/fsl,imx-se-fw.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX EdgeLock Enclave Firmware (ELEFW)
+
+maintainers:
+  - Pankaj Gupta <pankaj.gupta@nxp.com>
+
+description:
+  The NXP's i.MX EdgeLock Enclave, a HW IP creating an embedded
+  secure enclave within the SoC boundary to enable features like
+  - HSM
+  - SHE
+  - V2X
+
+  It uses message unit to communicate and coordinate to pass messages
+  (e.g., data,  status and control) through its interfaces.
+
+properties:
+  compatible:
+    enum:
+      - fsl,imx8ulp-se-fw
+      - fsl,imx93-se-fw
+
+  mboxes:
+    description:
+      All MU channels must be within the same MU instance. Cross instances are
+      not allowed. Users need to ensure that used MU instance does not conflict
+      with other execution environments.
+    items:
+      - description: TX0 MU channel
+      - description: RX0 MU channel
+
+  mbox-names:
+    items:
+      - const: tx
+      - const: rx
+
+  fsl,mu-id:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Identifier to the message-unit among the multiple message-unit that exists on SoC.
+      Per message-unit, multiple misc-devices are created, that are  used by userspace
+      application as logical-waiter and logical-receiver.
+
+  memory-region:
+    items:
+      - description: Reserved memory region that can be accessed by firmware. Used for
+          exchanging the buffers between driver and firmware.
+
+  fsl,sram:
+    description: Phandle to the device SRAM
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+
+required:
+  - compatible
+  - mboxes
+  - mbox-names
+  - fsl,mu-id
+
+additionalProperties: false
+
+examples:
+  - |
+    ele_fw: se-fw {
+      compatible = "fsl,imx8ulp-se-fw";
+      mbox-names = "tx", "rx";
+      mboxes = <&s4muap 0 0>, <&s4muap 1 0>;
+      fsl,mu-id = <2>;
+    };