| Message ID | 20230911060200.2164771-2-danishanwar@ti.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | Add Half Duplex support for ICSSG Driver | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On Mon, Sep 11, 2023 at 11:31:59AM +0530, MD Danish Anwar wrote: > In order to support half-duplex operation at 10M and 100M link speeds, the > PHY collision detection signal (COL) should be routed to ICSSG > GPIO pin (PRGx_PRU0/1_GPI10) so that firmware can detect collision signal > and apply the CSMA/CD algorithm applicable for half duplex operation. A DT > property, "ti,half-duplex-capable" is introduced for this purpose. If > board has PHY COL pin conencted to PRGx_PRU1_GPIO10, this DT property can > be added to eth node of ICSSG, MII port to support half duplex operation at > that port. > > Reviewed-by: Roger Quadros <rogerq@kernel.org> > Signed-off-by: MD Danish Anwar <danishanwar@ti.com> > --- > Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml b/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml > index 311c570165f9..bba17d4d5874 100644 > --- a/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml > +++ b/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml > @@ -106,6 +106,13 @@ properties: > phandle to system controller node and register offset > to ICSSG control register for RGMII transmit delay > > + ti,half-duplex-capable: > + type: boolean > + description: > + Enable half duplex operation on ICSSG MII port. This requires Still have capable vs. enable confusion. Please reword the description. > + PHY output pin (COL) to be routed to ICSSG GPIO pin > + (PRGx_PRU0/1_GPIO10) as input. > + > required: > - reg > anyOf: > -- > 2.34.1 >
On 11/09/23 22:16, Rob Herring wrote: > On Mon, Sep 11, 2023 at 11:31:59AM +0530, MD Danish Anwar wrote: >> In order to support half-duplex operation at 10M and 100M link speeds, the >> PHY collision detection signal (COL) should be routed to ICSSG >> GPIO pin (PRGx_PRU0/1_GPI10) so that firmware can detect collision signal >> and apply the CSMA/CD algorithm applicable for half duplex operation. A DT >> property, "ti,half-duplex-capable" is introduced for this purpose. If >> board has PHY COL pin conencted to PRGx_PRU1_GPIO10, this DT property can >> be added to eth node of ICSSG, MII port to support half duplex operation at >> that port. >> >> Reviewed-by: Roger Quadros <rogerq@kernel.org> >> Signed-off-by: MD Danish Anwar <danishanwar@ti.com> >> --- >> Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml | 7 +++++++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml b/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml >> index 311c570165f9..bba17d4d5874 100644 >> --- a/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml >> +++ b/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml >> @@ -106,6 +106,13 @@ properties: >> phandle to system controller node and register offset >> to ICSSG control register for RGMII transmit delay >> >> + ti,half-duplex-capable: >> + type: boolean >> + description: >> + Enable half duplex operation on ICSSG MII port. This requires > > Still have capable vs. enable confusion. Please reword the description. > Sure Rob, I will change the description to below. description: Indicates that the PHY output pin (COL) is routed to ICSSG GPIO pin (PRGx_PRU0/1_GPIO10) as input and ICSSG MII port is capable of half duplex operations. Please let me know if this looks OK or if any other change is required. >> + PHY output pin (COL) to be routed to ICSSG GPIO pin >> + (PRGx_PRU0/1_GPIO10) as input. >> + >> required: >> - reg >> anyOf: >> -- >> 2.34.1 >>
> Sure Rob, I will change the description to below. > > description: > Indicates that the PHY output pin (COL) is routed to ICSSG GPIO The PHY has multiple output pins, so i would not put COL in brackets, but make it explicit which pin you are referring to. > pin (PRGx_PRU0/1_GPIO10) as input and ICSSG MII port is capable > of half duplex operations. "input and so the ICSSG MII port is" Andrew
On 12/09/23 20:46, Andrew Lunn wrote: >> Sure Rob, I will change the description to below. >> >> description: >> Indicates that the PHY output pin (COL) is routed to ICSSG GPIO > > The PHY has multiple output pins, so i would not put COL in brackets, > but make it explicit which pin you are referring to. > Sure, I will remove the brackets and make it explicit. >> pin (PRGx_PRU0/1_GPIO10) as input and ICSSG MII port is capable >> of half duplex operations. > > "input and so the ICSSG MII port is" > I think "input so that the ICSSG MII port is" will be better. The description would look something like below, description: Indicates that the PHY output pin COL is routed to ICSSG GPIO pin (PRGx_PRU0/1_GPIO10) as input so that the ICSSG MII port is capable of half duplex operations. I will post the next version with this change. > Andrew
On Mon, Sep 11, 2023 at 11:31:59AM +0530, MD Danish Anwar wrote: > In order to support half-duplex operation at 10M and 100M link speeds, the > PHY collision detection signal (COL) should be routed to ICSSG > GPIO pin (PRGx_PRU0/1_GPI10) so that firmware can detect collision signal > and apply the CSMA/CD algorithm applicable for half duplex operation. A DT > property, "ti,half-duplex-capable" is introduced for this purpose. If > board has PHY COL pin conencted to PRGx_PRU1_GPIO10, this DT property can nit: connected ...
diff --git a/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml b/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml index 311c570165f9..bba17d4d5874 100644 --- a/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml +++ b/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml @@ -106,6 +106,13 @@ properties: phandle to system controller node and register offset to ICSSG control register for RGMII transmit delay + ti,half-duplex-capable: + type: boolean + description: + Enable half duplex operation on ICSSG MII port. This requires + PHY output pin (COL) to be routed to ICSSG GPIO pin + (PRGx_PRU0/1_GPIO10) as input. + required: - reg anyOf: