| Message ID | 20230622-topic-8998clk-v1-1-5b7a0d6e98b1@linaro.org |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | MSM8998 clk cleanups and fixups | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success |
On 6/22/2023 5:57 AM, Konrad Dybcio wrote: > GPLL0 has two separate outputs to both GPUSS and MMSS: one that's > 2-divided and one that runs at the same rate as the GPLL0 itself. > > Add the missing ones to the binding. > > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
On 22/06/2023 13:57, Konrad Dybcio wrote: > GPLL0 has two separate outputs to both GPUSS and MMSS: one that's > 2-divided and one that runs at the same rate as the GPLL0 itself. > > Add the missing ones to the binding. > > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h index 1badb4f9c58f..b5456a64d421 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8998.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h @@ -190,6 +190,9 @@ #define AGGRE2_SNOC_NORTH_AXI 181 #define SSC_XO 182 #define SSC_CNOC_AHBS_CLK 183 +#define GCC_MMSS_GPLL0_DIV_CLK 184 +#define GCC_GPU_GPLL0_DIV_CLK 185 +#define GCC_GPU_GPLL0_CLK 186 #define PCIE_0_GDSC 0 #define UFS_GDSC 1
GPLL0 has two separate outputs to both GPUSS and MMSS: one that's 2-divided and one that runs at the same rate as the GPLL0 itself. Add the missing ones to the binding. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- include/dt-bindings/clock/qcom,gcc-msm8998.h | 3 +++ 1 file changed, 3 insertions(+)