| Message ID | 20230421124150.21190-2-quic_devipriy@quicinc.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Add support for PCIe PHY in IPQ9574 | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dt-meta-schema | fail | build log |
On Fri, 21 Apr 2023 18:11:49 +0530, Devi Priya wrote: > Add bindings for the PCIe QMP PHYs found on IPQ9574. > > Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> > --- > Changes in V1: > - Introduced a new binding for ipq9574 as suggested by Krzysztof > > .../phy/qcom,ipq9574-qmp-pcie-phy.yaml | 90 +++++++++++++++++++ > 1 file changed, 90 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.example.dts:18:18: fatal error: dt-bindings/clock/qcom,ipq9574-gcc.h: No such file or directory 18 | #include <dt-bindings/clock/qcom,ipq9574-gcc.h> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. make[1]: *** [scripts/Makefile.lib:419: Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.example.dtb] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1512: dt_binding_check] Error 2 doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230421124150.21190-2-quic_devipriy@quicinc.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
On 21/04/2023 14:41, Devi Priya wrote: > Add bindings for the PCIe QMP PHYs found on IPQ9574. > > Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> > --- > Changes in V1: > - Introduced a new binding for ipq9574 as suggested by Krzysztof It looks it depends on the clock header. Either mention the dependency here or better convert the clock IDs to numerical values. With the second approach the patch can be applied independently from clock headers patch. > > .../phy/qcom,ipq9574-qmp-pcie-phy.yaml | 90 +++++++++++++++++++ > 1 file changed, 90 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml > Assuming you tested it (as Rob's bot cannot due to dependency): Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On 4/21/2023 10:19 PM, Krzysztof Kozlowski wrote: > On 21/04/2023 14:41, Devi Priya wrote: >> Add bindings for the PCIe QMP PHYs found on IPQ9574. >> >> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> >> --- >> Changes in V1: >> - Introduced a new binding for ipq9574 as suggested by Krzysztof > > It looks it depends on the clock header. > > Either mention the dependency here or better convert the clock IDs to > numerical values. With the second approach the patch can be applied > independently from clock headers patch. Got it. will use numerical values for clock IDs. Just to mention, it depends on the below series which is merged in linux-next/master https://patchwork.kernel.org/project/linux-arm-msm/cover/20230316072940.29137-1-quic_devipriy@quicinc.com/ > >> >> .../phy/qcom,ipq9574-qmp-pcie-phy.yaml | 90 +++++++++++++++++++ >> 1 file changed, 90 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml >> > > Assuming you tested it (as Rob's bot cannot due to dependency): > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Yup, thanks! > > Best regards, > Krzysztof >
diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml new file mode 100644 index 000000000000..7c8012647051 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,ipq9574-qmp-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QMP PHY controller (PCIe, IPQ9574) + +maintainers: + - Vinod Koul <vkoul@kernel.org> + +description: + The QMP PHY controller supports physical layer functionality for a number of + controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. + +properties: + compatible: + enum: + - qcom,ipq9574-qmp-gen3x1-pcie-phy + - qcom,ipq9574-qmp-gen3x2-pcie-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 5 + + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: anoc_lane + - const: snoc_lane + - const: pipe + + resets: + maxItems: 2 + + reset-names: + items: + - const: phy + - const: common + + "#clock-cells": + const: 0 + + clock-output-names: + maxItems: 1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - "#clock-cells" + - clock-output-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,ipq9574-gcc.h> + #include <dt-bindings/reset/qcom,ipq9574-gcc.h> + + pcie0_phy: phy@84000 { + compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; + reg = <0x00084000 0x1000>; + + clocks = <&gcc GCC_PCIE0_AUX_CLK>, + <&gcc GCC_PCIE0_AHB_CLK>, + <&gcc GCC_ANOC_PCIE0_1LANE_M_CLK>, + <&gcc GCC_SNOC_PCIE0_1LANE_S_CLK>, + <&gcc GCC_PCIE0_PIPE_CLK>; + clock-names = "aux", "cfg_ahb", "anoc_lane", "snoc_lane", "pipe"; + + resets = <&gcc GCC_PCIE0_PHY_BCR>, + <&gcc GCC_PCIE0PHY_PHY_BCR>; + reset-names = "phy", "common"; + + #clock-cells = <0>; + clock-output-names = "gcc_pcie0_pipe_clk_src"; + + #phy-cells = <0>; + };
Add bindings for the PCIe QMP PHYs found on IPQ9574. Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> --- Changes in V1: - Introduced a new binding for ipq9574 as suggested by Krzysztof .../phy/qcom,ipq9574-qmp-pcie-phy.yaml | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq9574-qmp-pcie-phy.yaml