| Message ID | 20230323090822.61766-2-angelogioacchino.delregno@collabora.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Panfrost: GPU Speed-binning support via OPP | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On 23/03/2023 10:08, AngeloGioacchino Del Regno wrote: > Some SoCs implementing ARM Mali GPUs may be subject to speed binning > and the usable bin is read from nvmem: document the addition of nvmem > and nvmem-cells for 'speed-bin'. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index 8a0083800810..1eecb014016c 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -104,6 +104,13 @@ properties: dma-coherent: true + nvmem-cell-names: + items: + - const: speed-bin + + nvmem-cells: + maxItems: 1 + required: - compatible - reg
Some SoCs implementing ARM Mali GPUs may be subject to speed binning and the usable bin is read from nvmem: document the addition of nvmem and nvmem-cells for 'speed-bin'. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- .../devicetree/bindings/gpu/arm,mali-bifrost.yaml | 7 +++++++ 1 file changed, 7 insertions(+)