| Message ID | 20230315064726.22739-1-biju.das.jz@bp.renesas.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | [1/2] dt-bindings: dma: rz-dmac: Document clock-names and reset-names | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On 15/03/2023 07:47, Biju Das wrote: > Document clock-names and reset-names properties as we have multiple > clocks and resets. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > .../devicetree/bindings/dma/renesas,rz-dmac.yaml | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml > index f638d3934e71..c284abc6784a 100644 > --- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml > +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml > @@ -54,6 +54,11 @@ properties: > - description: DMA main clock > - description: DMA register access clock > > + clock-names: > + items: > + - const: main > + - const: register > + > '#dma-cells': > const: 1 > description: > @@ -77,16 +82,23 @@ properties: > - description: Reset for DMA ARESETN reset terminal > - description: Reset for DMA RST_ASYNC reset terminal > > + reset-names: > + items: > + - const: arst > + - const: rst_async > + > required: > - compatible > - reg > - interrupts > - interrupt-names > - clocks > + - clock-names > - '#dma-cells' > - dma-channels > - power-domains > - resets > + - reset-names The clock and reset entries are ordered anyway, so requiring '-names' is not really necessary. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On 15-03-23, 06:47, Biju Das wrote: > Document clock-names and reset-names properties as we have multiple > clocks and resets. Applied, thanks
On Wed, Mar 15, 2023 at 7:47 AM Biju Das <biju.das.jz@bp.renesas.com> wrote: > Add clock-names and reset-names to RZ/G2{L,LC,UL}, RZ/V2L and > RZ/Five DMAC nodes. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v6.4. Gr{oetje,eeting}s, Geert
diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml index f638d3934e71..c284abc6784a 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml @@ -54,6 +54,11 @@ properties: - description: DMA main clock - description: DMA register access clock + clock-names: + items: + - const: main + - const: register + '#dma-cells': const: 1 description: @@ -77,16 +82,23 @@ properties: - description: Reset for DMA ARESETN reset terminal - description: Reset for DMA RST_ASYNC reset terminal + reset-names: + items: + - const: arst + - const: rst_async + required: - compatible - reg - interrupts - interrupt-names - clocks + - clock-names - '#dma-cells' - dma-channels - power-domains - resets + - reset-names additionalProperties: false @@ -124,9 +136,11 @@ examples: "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>, <&cpg CPG_MOD R9A07G044_DMAC_PCLK>; + clock-names = "main", "register"; power-domains = <&cpg>; resets = <&cpg R9A07G044_DMAC_ARESETN>, <&cpg R9A07G044_DMAC_RST_ASYNC>; + reset-names = "arst", "rst_async"; #dma-cells = <1>; dma-channels = <16>; };
Document clock-names and reset-names properties as we have multiple clocks and resets. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- .../devicetree/bindings/dma/renesas,rz-dmac.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+)