| Message ID | 20230222153251.254492-3-manivannan.sadhasivam@linaro.org |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | Add PCIe RC support to Qcom SDX55 SoC | expand |
On 22/02/2023 16:32, Manivannan Sadhasivam wrote: > Most of the PCIe controllers require iommu support to function properly. > So let's add them to the binding. > If most of them require iommu, why not adding it as a required property to respective (or new) "if:then:" part? Best regards, Krzysztof
On Thu, Feb 23, 2023 at 10:37:27AM +0100, Krzysztof Kozlowski wrote: > On 22/02/2023 16:32, Manivannan Sadhasivam wrote: > > Most of the PCIe controllers require iommu support to function properly. > > So let's add them to the binding. > > > > If most of them require iommu, why not adding it as a required property > to respective (or new) "if:then:" part? > Well, I thought about it but then followed the convention of "dma-coherent" property. I asked this same question while adding that property but I didn't get a clear answer (or maybe I missed something). So if you want me to add iommu properties to individual SoCs, then please explain why the same cannot be done for "dma-coherent" as not all SoCs support dma coherency for PCIe controllers. Thanks, Mani > Best regards, > Krzysztof >
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index a3639920fcbb..f48d0792aa57 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -64,6 +64,11 @@ properties: dma-coherent: true + iommus: + maxItems: 1 + + iommu-map: true + interconnects: maxItems: 2
Most of the PCIe controllers require iommu support to function properly. So let's add them to the binding. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 5 +++++ 1 file changed, 5 insertions(+)