| Message ID | 20221207055405.30940-12-hayashi.kunihiko@socionext.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | dt-bindings: soc: Introduce UniPhier miscellaneous register blocks and fix examples | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On Wed, 07 Dec 2022 14:54:00 +0900, Kunihiko Hayashi wrote: > Add devicetree binding schema for the peripheral block implemented on > Socionext Uniphier SoCs. > > Peripheral block implemented on Socionext UniPhier SoCs is an integrated > component of the peripherals including UART, I2C/FI2C, and SCSSI. > > Peripheral block has some function logics to control the component. > > Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> > --- > .../socionext,uniphier-perictrl.yaml | 65 +++++++++++++++++++ > 1 file changed, 65 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml > Running 'make dtbs_check' with the schema in this patch gives the following warnings. Consider if they are expected or the schema is incorrect. These may not be new warnings. Note that it is not yet a requirement to have 0 warnings for dtbs_check. This will change in the future. Full log is available here: https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20221207055405.30940-12-hayashi.kunihiko@socionext.com perictrl@59820000: 'clock', 'reset' do not match any of the regexes: '^clock-controller(@[0-9a-f]+)?$', '^reset-controller(@[0-9a-f]+)?$', 'pinctrl-[0-9]+' arch/arm64/boot/dts/socionext/uniphier-ld11-global.dtb arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dtb arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dtb arch/arm64/boot/dts/socionext/uniphier-ld20-global.dtb arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dtb arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dtb arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget0.dtb arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget1.dtb arch/arm/boot/dts/uniphier-ld4-ref.dtb arch/arm/boot/dts/uniphier-ld6b-ref.dtb arch/arm/boot/dts/uniphier-pro4-ace.dtb arch/arm/boot/dts/uniphier-pro4-ref.dtb arch/arm/boot/dts/uniphier-pro4-sanji.dtb arch/arm/boot/dts/uniphier-pxs2-gentil.dtb arch/arm/boot/dts/uniphier-pxs2-vodka.dtb arch/arm/boot/dts/uniphier-sld8-ref.dtb
diff --git a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml new file mode 100644 index 000000000000..23223a9fe76a --- /dev/null +++ b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-perictrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext UniPhier peripheral block controller + +maintainers: + - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> + +description: |+ + Peripheral block implemented on Socionext UniPhier SoCs is an integrated + component of the peripherals including UART, I2C/FI2C, and SCSSI. + Peripheral block controller is a logic to control the component. + +properties: + compatible: + items: + - enum: + - socionext,uniphier-ld4-perictrl + - socionext,uniphier-pro4-perictrl + - socionext,uniphier-pro5-perictrl + - socionext,uniphier-pxs2-perictrl + - socionext,uniphier-sld8-perictrl + - socionext,uniphier-ld11-perictrl + - socionext,uniphier-ld20-perictrl + - socionext,uniphier-pxs3-perictrl + - socionext,uniphier-nx1-perictrl + - const: simple-mfd + - const: syscon + + reg: + maxItems: 1 + +patternProperties: + "^clock-controller(@[0-9a-f]+)?$": + $ref: /schemas/clock/socionext,uniphier-clock.yaml# + + "^reset-controller(@[0-9a-f]+)?$": + $ref: /schemas/reset/socionext,uniphier-reset.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + syscon@59820000 { + compatible = "socionext,uniphier-ld20-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + clock-controller { + compatible = "socionext,uniphier-ld20-peri-clock"; + #clock-cells = <1>; + }; + + reset-controller { + compatible = "socionext,uniphier-ld20-peri-reset"; + #reset-cells = <1>; + }; + };
Add devicetree binding schema for the peripheral block implemented on Socionext Uniphier SoCs. Peripheral block implemented on Socionext UniPhier SoCs is an integrated component of the peripherals including UART, I2C/FI2C, and SCSSI. Peripheral block has some function logics to control the component. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> --- .../socionext,uniphier-perictrl.yaml | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml