| Message ID | 20221124135829.2551873-2-vadym.kochan@plvision.eu |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | PCI: armada8k: Add support for AC5 SoC | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success |
On 24/11/2022 14:58, Vadym Kochan wrote: > AC5 SoC has armada8k PCIe IP so add compatible string for it. > > Signed-off-by: Vadym Kochan <vadym.kochan@plvision.eu> > --- > v2: no changes Not correct... I wasted some time looking for v1. This is a new patch. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt index ff25a134befa..b272fa4f08b5 100644 --- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt +++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt @@ -4,7 +4,9 @@ This PCIe host controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in snps,dw-pcie.yaml. Required properties: -- compatible: "marvell,armada8k-pcie" +- compatible: Should be set to one of the following: + - "marvell,armada8k-pcie" : For A7K/8K family of SoCs + - "marvell,ac5-pcie" : For AC5 family of SoCs - reg: must contain two register regions - the control register region - the config space region
AC5 SoC has armada8k PCIe IP so add compatible string for it. Signed-off-by: Vadym Kochan <vadym.kochan@plvision.eu> --- v2: no changes Documentation/devicetree/bindings/pci/pci-armada8k.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)