| Message ID | 20221121105210.68596-2-shradha.t@samsung.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Add PCIe support for Tesla FSD SoC | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On 21/11/2022 11:52, Shradha Todi wrote: > Document the PCIe PHY device tree bindings for Tesla > FSD SoC Subject: drop second, redundant "bindings". > > Signed-off-by: Shradha Todi <shradha.t@samsung.com> > --- > .../bindings/phy/phy-tesla-pcie.yaml | 75 +++++++++++++++++++ > 1 file changed, 75 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/phy-tesla-pcie.yaml > > diff --git a/Documentation/devicetree/bindings/phy/phy-tesla-pcie.yaml b/Documentation/devicetree/bindings/phy/phy-tesla-pcie.yaml > new file mode 100644 > index 000000000000..8fa9a050af7a > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/phy-tesla-pcie.yaml Filename based on compatible. > @@ -0,0 +1,75 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/phy-tesla-pcie.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Tesla FSD SoC PCIe PHY > + > +maintainers: > + - Shradha Todi <shradha.t@samsung.com> > + > +properties: > + "#phy-cells": > + const: 0 Put compatible as first. > + > + compatible: > + enum: > + - tesla,fsd-pcie-phy > + > + reg: > + minItems: 2 Drop minItems > + maxItems: 2 > + > + reg-names: > + minItems: 2 > + maxItems: 2 Drop both. > + items: > + enum: [phy, pcs] Instead list items one after another. > + description: | > + phy is the register access to PMA layer > + pcs is the register access to PCS layer These go to describing items in 'reg:' > + > + phy-mode: > + description: | > + Defines the bifurcation mode of the PHY enum, probably type as well... phy-mode is usually a string. Is it here? > + > + tesla,pmureg-phandle: Drop phandle, so tesla,pmu-syscon > + $ref: '/schemas/types.yaml#/definitions/phandle' Drop quotes > + description: phandle for PMU system controller interface used to > + control PMU register bits for PCIe PHY > + > + tesla,pcie-sysreg: > + $ref: '/schemas/types.yaml#/definitions/phandle' Drop quotes > + description: phandle for system control registers, used to > + control phy signals at system level > + > +required: > + - "#phy-cells" > + - compatible compatible first. > + - reg > + - reg-names > + - phy-mode > + - tesla,pmureg-phandle > + - tesla,pcie-sysreg > + > +additionalProperties: false > + > +examples: > + - | > + bus { > + #address-cells = <2>; > + #size-cells = <2>; > + > + pcie_phy0: pcie-phy@15080000 { > + compatible = "tesla,fsd-pcie-phy"; > + #phy-cells = <0>; > + reg = <0x0 0x15080000 0x0 0x2000>, <0x0 0x150A0000 0x0 0x1000>; > + reg-names = "phy", "pcs"; > + tesla,pmureg-phandle = <&pmu_system_controller>; > + tesla,pcie-sysreg = <&sysreg_fsys0>; > + phy-mode = <0>; > + status = "disabled"; Drop status > + }; > + }; > +... Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/phy/phy-tesla-pcie.yaml b/Documentation/devicetree/bindings/phy/phy-tesla-pcie.yaml new file mode 100644 index 000000000000..8fa9a050af7a --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-tesla-pcie.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/phy-tesla-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tesla FSD SoC PCIe PHY + +maintainers: + - Shradha Todi <shradha.t@samsung.com> + +properties: + "#phy-cells": + const: 0 + + compatible: + enum: + - tesla,fsd-pcie-phy + + reg: + minItems: 2 + maxItems: 2 + + reg-names: + minItems: 2 + maxItems: 2 + items: + enum: [phy, pcs] + description: | + phy is the register access to PMA layer + pcs is the register access to PCS layer + + phy-mode: + description: | + Defines the bifurcation mode of the PHY + + tesla,pmureg-phandle: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: phandle for PMU system controller interface used to + control PMU register bits for PCIe PHY + + tesla,pcie-sysreg: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: phandle for system control registers, used to + control phy signals at system level + +required: + - "#phy-cells" + - compatible + - reg + - reg-names + - phy-mode + - tesla,pmureg-phandle + - tesla,pcie-sysreg + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie_phy0: pcie-phy@15080000 { + compatible = "tesla,fsd-pcie-phy"; + #phy-cells = <0>; + reg = <0x0 0x15080000 0x0 0x2000>, <0x0 0x150A0000 0x0 0x1000>; + reg-names = "phy", "pcs"; + tesla,pmureg-phandle = <&pmu_system_controller>; + tesla,pcie-sysreg = <&sysreg_fsys0>; + phy-mode = <0>; + status = "disabled"; + }; + }; +...
Document the PCIe PHY device tree bindings for Tesla FSD SoC Signed-off-by: Shradha Todi <shradha.t@samsung.com> --- .../bindings/phy/phy-tesla-pcie.yaml | 75 +++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-tesla-pcie.yaml