| Message ID | 20221118131641.469238-3-biju.das.jz@bp.renesas.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Add RZ/V2{M, MA} driver support | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On 18/11/2022 14:16, Biju Das wrote: > Add device tree bindings for the RZ/V2{M, MA} PWM Timer (PWM). > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Thank you for your patch. There is something to discuss/improve. > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - power-domains > + > +if: > + properties: > + compatible: > + contains: > + enum: > + - renesas,r9a09g055-pwm > +then: > + required: > + - resets > + > +allOf: > + - $ref: pwm.yaml# Put the if under allOf: allOf: - $ref... - if: then: This allows easier growth. With above: Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
Hi Krzysztof Kozlowski, thanks for the feedback. > Subject: Re: [PATCH 2/5] dt-bindings: pwm: Add RZ/V2M PWM binding > > On 18/11/2022 14:16, Biju Das wrote: > > Add device tree bindings for the RZ/V2{M, MA} PWM Timer (PWM). > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > Thank you for your patch. There is something to discuss/improve. > > > +required: > > + - compatible > > + - reg > > + - interrupts > > + - clocks > > + - clock-names > > + - power-domains > > + > > +if: > > + properties: > > + compatible: > > + contains: > > + enum: > > + - renesas,r9a09g055-pwm > > +then: > > + required: > > + - resets > > + > > +allOf: > > + - $ref: pwm.yaml# > > Put the if under allOf: > > allOf: > - $ref... > - if: > then: > > This allows easier growth. OK will send v2, along with feedback for driver patches if any. Cheers, Biju > > With above: > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > > Best regards, > Krzysztof
Hi Biju, On Fri, Nov 18, 2022 at 2:16 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > Add device tree bindings for the RZ/V2{M, MA} PWM Timer (PWM). > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Thanks for your patch! > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/renesas,rzv2m-pwm.yaml > @@ -0,0 +1,98 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/renesas,rzv2m-pwm.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/V2{M, MA} PWM Timer (PWM) > + > +maintainers: > + - Biju Das <biju.das.jz@bp.renesas.com> > + > +description: | > + The RZ/V2{M, MA} PWM Timer (PWM) composed of 16 channels. It supports the > + following functions > + * The PWM has 24-bit counters which operate at PWM_CLK (48 MHz). > + * The frequency division ratio for internal counter operation is selectable > + as PWM_CLK divided by 1, 16, 256, or 2048. > + * The period as well as the duty cycle is adjustable. > + * The low-level and high-level order of the PWM signals can be inverted. > + * The duty cycle of the PWM signal is selectable in the range from 0 to 100%. > + * The minimum resolution is 20.83 ns. > + * Three interrupt sources: Rising and falling edges of the PWM signal and > + clearing of the counter > + * Counter operation and the bus interface are asynchronous and both can > + operate independently of the magnitude relationship of the respective > + clock periods. > + > +properties: > + compatible: > + items: > + - enum: > + - renesas,r9a09g011-pwm # RZ/V2M > + - renesas,r9a09g055-pwm # RZ/V2MA > + - const: renesas,rzv2m-pwm > + > + reg: > + maxItems: 1 > + > + '#pwm-cells': > + const: 2 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + items: > + - description: CPU Peripheral Group F APB clock "APB clock" PWM0-7] are part of Peripheral Group E, and the block might be reused on SoCs not using CPU Peripheral Group clock signals. > + - description: PWM clock > + > + clock-names: > + items: > + - const: apb > + - const: pwm > + > + power-domains: > + maxItems: 1 > + > + resets: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - power-domains > + > +if: > + properties: > + compatible: > + contains: > + enum: > + - renesas,r9a09g055-pwm > +then: > + required: > + - resets I think you should make the resets property required unconditionally. DT describes hardware, not software policy. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, Thanks for the feedback. > Subject: Re: [PATCH 2/5] dt-bindings: pwm: Add RZ/V2M PWM binding > > Hi Biju, > > On Fri, Nov 18, 2022 at 2:16 PM Biju Das <biju.das.jz@bp.renesas.com> > wrote: > > Add device tree bindings for the RZ/V2{M, MA} PWM Timer (PWM). > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > Thanks for your patch! > > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pwm/renesas,rzv2m-pwm.yaml > > @@ -0,0 +1,98 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 > > +--- > > +$id: > > + > > +title: Renesas RZ/V2{M, MA} PWM Timer (PWM) > > + > > +maintainers: > > + - Biju Das <biju.das.jz@bp.renesas.com> > > + > > +description: | > > + The RZ/V2{M, MA} PWM Timer (PWM) composed of 16 channels. It > > +supports the > > + following functions > > + * The PWM has 24-bit counters which operate at PWM_CLK (48 MHz). > > + * The frequency division ratio for internal counter operation is > selectable > > + as PWM_CLK divided by 1, 16, 256, or 2048. > > + * The period as well as the duty cycle is adjustable. > > + * The low-level and high-level order of the PWM signals can be > inverted. > > + * The duty cycle of the PWM signal is selectable in the range from > 0 to 100%. > > + * The minimum resolution is 20.83 ns. > > + * Three interrupt sources: Rising and falling edges of the PWM > signal and > > + clearing of the counter > > + * Counter operation and the bus interface are asynchronous and both > can > > + operate independently of the magnitude relationship of the > respective > > + clock periods. > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - renesas,r9a09g011-pwm # RZ/V2M > > + - renesas,r9a09g055-pwm # RZ/V2MA > > + - const: renesas,rzv2m-pwm > > + > > + reg: > > + maxItems: 1 > > + > > + '#pwm-cells': > > + const: 2 > > + > > + interrupts: > > + maxItems: 1 > > + > > + clocks: > > + items: > > + - description: CPU Peripheral Group F APB clock > > "APB clock" Agreed. > > PWM0-7] are part of Peripheral Group E, and the block might be reused on > SoCs not using CPU Peripheral Group clock signals. > > > + - description: PWM clock > > + > > + clock-names: > > + items: > > + - const: apb > > + - const: pwm > > + > > + power-domains: > > + maxItems: 1 > > + > > + resets: > > + maxItems: 1 > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + - clocks > > + - clock-names > > + - power-domains > > + > > +if: > > + properties: > > + compatible: > > + contains: > > + enum: > > + - renesas,r9a09g055-pwm > > +then: > > + required: > > + - resets > > I think you should make the resets property required unconditionally. > DT describes hardware, not software policy. OK will send V2 with these changes. Cheers, Biju
diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzv2m-pwm.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzv2m-pwm.yaml new file mode 100644 index 000000000000..d615213357ad --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/renesas,rzv2m-pwm.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/renesas,rzv2m-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2{M, MA} PWM Timer (PWM) + +maintainers: + - Biju Das <biju.das.jz@bp.renesas.com> + +description: | + The RZ/V2{M, MA} PWM Timer (PWM) composed of 16 channels. It supports the + following functions + * The PWM has 24-bit counters which operate at PWM_CLK (48 MHz). + * The frequency division ratio for internal counter operation is selectable + as PWM_CLK divided by 1, 16, 256, or 2048. + * The period as well as the duty cycle is adjustable. + * The low-level and high-level order of the PWM signals can be inverted. + * The duty cycle of the PWM signal is selectable in the range from 0 to 100%. + * The minimum resolution is 20.83 ns. + * Three interrupt sources: Rising and falling edges of the PWM signal and + clearing of the counter + * Counter operation and the bus interface are asynchronous and both can + operate independently of the magnitude relationship of the respective + clock periods. + +properties: + compatible: + items: + - enum: + - renesas,r9a09g011-pwm # RZ/V2M + - renesas,r9a09g055-pwm # RZ/V2MA + - const: renesas,rzv2m-pwm + + reg: + maxItems: 1 + + '#pwm-cells': + const: 2 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: CPU Peripheral Group F APB clock + - description: PWM clock + + clock-names: + items: + - const: apb + - const: pwm + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + +if: + properties: + compatible: + contains: + enum: + - renesas,r9a09g055-pwm +then: + required: + - resets + +allOf: + - $ref: pwm.yaml# + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r9a09g011-cpg.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pwm8: pwm@a4010400 { + compatible = "renesas,r9a09g011-pwm", "renesas,rzv2m-pwm"; + reg = <0xa4010400 0x80>; + interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPF_PCLK>, + <&cpg CPG_MOD R9A09G011_PWM8_CLK>; + clock-names = "apb", "pwm"; + power-domains = <&cpg>; + #pwm-cells = <2>; + };
Add device tree bindings for the RZ/V2{M, MA} PWM Timer (PWM). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- .../bindings/pwm/renesas,rzv2m-pwm.yaml | 98 +++++++++++++++++++ 1 file changed, 98 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rzv2m-pwm.yaml