| Message ID | 20221107204934.32655-6-Sergey.Semin@baikalelectronics.ru |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | PCI: dwc: Add generic resources and Baikal-T1 support | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On Mon, 07 Nov 2022 23:49:19 +0300, Serge Semin wrote: > It's normal to have the DW PCIe RP/EP DT-nodes equipped with the explicit > PHY phandle references. There can be up to 16 PHYs attach in accordance > with the maximum number of supported PCIe lanes. Let's extend the common > DW PCIe controller schema with the 'phys' and 'phy-names' properties > definition. There two types PHY names are defined: preferred generic names > '^pcie[0-9]+$' and non-preferred vendor-specific names > '^pcie([0-9]+|-?phy[0-9]*)?$' so to match the names currently supported by > the DW PCIe platform drivers ("pcie": meson; "pciephy": qcom, imx6; > "pcie-phy": uniphier, rockchip, spear13xx; "pcie": intel-gw; "pcie-phy%d": > keystone, dra7xx; "pcie": histb, etc). > > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> > > --- > > Changelog v3: > - This is a new patch unpinned from the next one: > https://lore.kernel.org/linux-pci/20220503214638.1895-2-Sergey.Semin@baikalelectronics.ru/ > by the Rob' request. (@Rob) > > Changelog v5: > - Add a note about having line-based PHY phandles order. (@Rob) > - Prefer 'pcie[0-9]+' PHY-names over the rest of the cases. (@Rob) > > Changelog v6: > - Add the Nvidia Tegra194-specific "p2u-[0-7]" phy-names too. (@DT-tbot) > - Drop 'deprecated' keywords from the vendor-specific names. (@Rob) > --- > .../bindings/pci/snps,dw-pcie-common.yaml | 24 +++++++++++++++++++ > .../bindings/pci/snps,dw-pcie-ep.yaml | 3 +++ > .../devicetree/bindings/pci/snps,dw-pcie.yaml | 3 +++ > 3 files changed, 30 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml index 554c2804c608..91d24e400dfc 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml @@ -17,6 +17,30 @@ description: select: false properties: + phys: + description: + There can be up to the number of possible lanes PHYs specified placed in + the phandle array in the line-based order. Obviously each the specified + PHYs are supposed to be able to work in the PCIe mode with a speed + implied by the DWC PCIe controller they are attached to. + minItems: 1 + maxItems: 16 + + phy-names: + minItems: 1 + maxItems: 16 + oneOf: + - description: Generic PHY names + items: + pattern: '^pcie[0-9]+$' + - description: + Vendor-specific PHY names. Consider using the generic + names above for new bindings. + items: + oneOf: + - pattern: '^pcie(-?phy[0-9]*)?$' + - pattern: '^p2u-[0-7]$' + reset-gpio: deprecated: true description: diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml index 7d05dcba419b..dcd521aed213 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml @@ -52,4 +52,7 @@ examples: <0xdfc01000 0x0001000>, /* IP registers 2 */ <0xd0000000 0x2000000>; /* Configuration space */ reg-names = "dbi", "dbi2", "addr_space"; + + phys = <&pcie_phy0>, <&pcie_phy1>, <&pcie_phy2>, <&pcie_phy3>; + phy-names = "pcie0", "pcie1", "pcie2", "pcie3"; }; diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml index 3fdc80453a85..d9512f7f7124 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml @@ -70,5 +70,8 @@ examples: reset-gpios = <&port0 0 1>; + phys = <&pcie_phy>; + phy-names = "pcie"; + num-lanes = <1>; };
It's normal to have the DW PCIe RP/EP DT-nodes equipped with the explicit PHY phandle references. There can be up to 16 PHYs attach in accordance with the maximum number of supported PCIe lanes. Let's extend the common DW PCIe controller schema with the 'phys' and 'phy-names' properties definition. There two types PHY names are defined: preferred generic names '^pcie[0-9]+$' and non-preferred vendor-specific names '^pcie([0-9]+|-?phy[0-9]*)?$' so to match the names currently supported by the DW PCIe platform drivers ("pcie": meson; "pciephy": qcom, imx6; "pcie-phy": uniphier, rockchip, spear13xx; "pcie": intel-gw; "pcie-phy%d": keystone, dra7xx; "pcie": histb, etc). Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> --- Changelog v3: - This is a new patch unpinned from the next one: https://lore.kernel.org/linux-pci/20220503214638.1895-2-Sergey.Semin@baikalelectronics.ru/ by the Rob' request. (@Rob) Changelog v5: - Add a note about having line-based PHY phandles order. (@Rob) - Prefer 'pcie[0-9]+' PHY-names over the rest of the cases. (@Rob) Changelog v6: - Add the Nvidia Tegra194-specific "p2u-[0-7]" phy-names too. (@DT-tbot) - Drop 'deprecated' keywords from the vendor-specific names. (@Rob) --- .../bindings/pci/snps,dw-pcie-common.yaml | 24 +++++++++++++++++++ .../bindings/pci/snps,dw-pcie-ep.yaml | 3 +++ .../devicetree/bindings/pci/snps,dw-pcie.yaml | 3 +++ 3 files changed, 30 insertions(+)