| Message ID | 20221104145938.1782464-3-biju.das.jz@bp.renesas.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Add support for linking gpt with poeg | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On 04/11/2022 10:59, Biju Das wrote: > RZ/G2L GPT IP supports output pin disable function by dead time > error and detecting short-circuits between output pins. > > Add documentation for the optional property renesas,poegs to > link a pair of GPT IOs with POEG. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > .../bindings/pwm/renesas,rzg2l-gpt.yaml | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml > index 620d5ae4ae30..32f9deae89e5 100644 > --- a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml > +++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml > @@ -245,6 +245,24 @@ properties: > resets: > maxItems: 1 > > + renesas,poegs: > + $ref: "/schemas/types.yaml#/definitions/phandle-array" No need for quotes. > + items: You miss here maxItems... but if you have just one item, then below "items" should be " - items" > + items: > + - description: phandle to POEG instance that serves the output disable > + - description: An index identifying pair of GPT channels. > + <0> - GPT channels 0 and 1 > + <1> - GPT channels 2 and 3 > + <2> - GPT channels 4 and 5 > + <3> - GPT channels 6 and 7 > + <4> - GPT channels 8 and 9 > + <5> - GPT channels 10 and 11 > + <6> - GPT channels 12 and 13 > + <7> - GPT channels 14 and 15 then this could bave enum or minimum/maximum. Can you try if these work? > + description: > + A list of phandle and channel index pair tuples to the POEGs that handle the > + output disable for the GPT channels. > + > required: > - compatible > - reg > @@ -375,4 +393,5 @@ examples: > power-domains = <&cpg>; > resets = <&cpg R9A07G044_GPT_RST_C>; > #pwm-cells = <2>; > + renesas,poegs = <&poeggd 4>; > }; Best regards, Krzysztof
Hi Krzysztof Kozlowski, Thanks for the feedback. > Subject: Re: [PATCH 2/3] dt-bindings: pwm: rzg2l-gpt: Document > renesas,poegs property > > On 04/11/2022 10:59, Biju Das wrote: > > RZ/G2L GPT IP supports output pin disable function by dead time > error > > and detecting short-circuits between output pins. > > > > Add documentation for the optional property renesas,poegs to link a > > pair of GPT IOs with POEG. > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > --- > > .../bindings/pwm/renesas,rzg2l-gpt.yaml | 19 > +++++++++++++++++++ > > 1 file changed, 19 insertions(+) > > > > diff --git > > a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml > > b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml > > index 620d5ae4ae30..32f9deae89e5 100644 > > --- a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml > > +++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml > > @@ -245,6 +245,24 @@ properties: > > resets: > > maxItems: 1 > > > > + renesas,poegs: > > + $ref: "/schemas/types.yaml#/definitions/phandle-array" > > No need for quotes. OK, I just referred renesas,vsps in [1] as example [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/display/renesas,du.yaml?h=v6.1-rc3#n85 > > > + items: > > You miss here maxItems... but if you have just one item, then below > "items" should be " - items" Max Items is 8, as we have 8 GPT hw channels. Based on HW board design, we should have flexibility to define something like below, renesas,poegs = <&poegga 0>, <&poeggb 1> <&poegga 2> <&poeggd 4>; > > > + items: > > + - description: phandle to POEG instance that serves the > output disable > > + - description: An index identifying pair of GPT channels. > > + <0> - GPT channels 0 and 1 > > + <1> - GPT channels 2 and 3 > > + <2> - GPT channels 4 and 5 > > + <3> - GPT channels 6 and 7 > > + <4> - GPT channels 8 and 9 > > + <5> - GPT channels 10 and 11 > > + <6> - GPT channels 12 and 13 > > + <7> - GPT channels 14 and 15 > > then this could bave enum or minimum/maximum. Can you try if these > work? OK, I will try second items as enum as it is predefined values and Will let you know the results. Cheers, Biju
Hi Krzysztof Kozlowski, > -----Original Message----- > From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Subject: Re: [PATCH 2/3] dt-bindings: pwm: rzg2l-gpt: Document > renesas,poegs property > > On 04/11/2022 10:59, Biju Das wrote: > > RZ/G2L GPT IP supports output pin disable function by dead time > error > > and detecting short-circuits between output pins. > > > > Add documentation for the optional property renesas,poegs to link a > > pair of GPT IOs with POEG. > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > --- > > .../bindings/pwm/renesas,rzg2l-gpt.yaml | 19 > +++++++++++++++++++ > > 1 file changed, 19 insertions(+) > > > > diff --git > > a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml > > b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml > > index 620d5ae4ae30..32f9deae89e5 100644 > > --- a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml > > +++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml > > @@ -245,6 +245,24 @@ properties: > > resets: > > maxItems: 1 > > > > + renesas,poegs: > > + $ref: "/schemas/types.yaml#/definitions/phandle-array" > > No need for quotes. > > > + items: > > You miss here maxItems... but if you have just one item, then below > "items" should be " - items" > > > + items: > > + - description: phandle to POEG instance that serves the > output disable > > + - description: An index identifying pair of GPT channels. > > + <0> - GPT channels 0 and 1 > > + <1> - GPT channels 2 and 3 > > + <2> - GPT channels 4 and 5 > > + <3> - GPT channels 6 and 7 > > + <4> - GPT channels 8 and 9 > > + <5> - GPT channels 10 and 11 > > + <6> - GPT channels 12 and 13 > > + <7> - GPT channels 14 and 15 > > then this could bave enum or minimum/maximum. Can you try if these > work? Yes, checks are passing with below changes. Will send V2 later once I get feedback for driver changes/ from other reviewers. renesas,poegs: - $ref: "/schemas/types.yaml#/definitions/phandle-array" + $ref: /schemas/types.yaml#/definitions/phandle-array items: + maxItems: 8 items: - description: phandle to POEG instance that serves the output disable - - description: An index identifying pair of GPT channels. - <0> - GPT channels 0 and 1 - <1> - GPT channels 2 and 3 - <2> - GPT channels 4 and 5 - <3> - GPT channels 6 and 7 - <4> - GPT channels 8 and 9 - <5> - GPT channels 10 and 11 - <6> - GPT channels 12 and 13 - <7> - GPT channels 14 and 15 + - enum: [ 0, 1, 2, 3, 4, 5, 6, 7 ] + description: | + An index identifying pair of GPT channels. + <0> : GPT channels 0 and 1 + <1> : GPT channels 2 and 3 + <2> : GPT channels 4 and 5 + <3> : GPT channels 6 and 7 + <4> : GPT channels 8 and 9 + <5> : GPT channels 10 and 11 + <6> : GPT channels 12 and 13 + <7> : GPT channels 14 and 15 Cheers, Biju
On 04/11/2022 12:52, Biju Das wrote: > Hi Krzysztof Kozlowski, > >> -----Original Message----- >> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> Subject: Re: [PATCH 2/3] dt-bindings: pwm: rzg2l-gpt: Document >> renesas,poegs property >> >> On 04/11/2022 10:59, Biju Das wrote: >>> RZ/G2L GPT IP supports output pin disable function by dead time >> error >>> and detecting short-circuits between output pins. >>> >>> Add documentation for the optional property renesas,poegs to link a >>> pair of GPT IOs with POEG. >>> >>> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> >>> --- >>> .../bindings/pwm/renesas,rzg2l-gpt.yaml | 19 >> +++++++++++++++++++ >>> 1 file changed, 19 insertions(+) >>> >>> diff --git >>> a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml >>> b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml >>> index 620d5ae4ae30..32f9deae89e5 100644 >>> --- a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml >>> +++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml >>> @@ -245,6 +245,24 @@ properties: >>> resets: >>> maxItems: 1 >>> >>> + renesas,poegs: >>> + $ref: "/schemas/types.yaml#/definitions/phandle-array" >> >> No need for quotes. >> >>> + items: >> >> You miss here maxItems... but if you have just one item, then below >> "items" should be " - items" >> >>> + items: >>> + - description: phandle to POEG instance that serves the >> output disable >>> + - description: An index identifying pair of GPT channels. >>> + <0> - GPT channels 0 and 1 >>> + <1> - GPT channels 2 and 3 >>> + <2> - GPT channels 4 and 5 >>> + <3> - GPT channels 6 and 7 >>> + <4> - GPT channels 8 and 9 >>> + <5> - GPT channels 10 and 11 >>> + <6> - GPT channels 12 and 13 >>> + <7> - GPT channels 14 and 15 >> >> then this could bave enum or minimum/maximum. Can you try if these >> work? > > Yes, checks are passing with below changes. > Will send V2 later once I get feedback for driver changes/ from other reviewers. > > renesas,poegs: > - $ref: "/schemas/types.yaml#/definitions/phandle-array" > + $ref: /schemas/types.yaml#/definitions/phandle-array > items: > + maxItems: 8 and it might also require minItems: 1 Thank you for changes. Best regards, Krzysztof
Hi Krzysztof Kozlowski, > -----Original Message----- > From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Sent: 04 November 2022 17:11 > To: Biju Das <biju.das.jz@bp.renesas.com>; Thierry Reding > <thierry.reding@gmail.com>; Rob Herring <robh+dt@kernel.org>; Krzysztof > Kozlowski <krzysztof.kozlowski+dt@linaro.org> > Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>; linux- > pwm@vger.kernel.org; devicetree@vger.kernel.org; Geert Uytterhoeven > <geert+renesas@glider.be>; Chris Paterson <Chris.Paterson2@renesas.com>; > Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>; linux- > renesas-soc@vger.kernel.org > Subject: Re: [PATCH 2/3] dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs > property > > On 04/11/2022 12:52, Biju Das wrote: > > Hi Krzysztof Kozlowski, > > > >> -----Original Message----- > >> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > >> Subject: Re: [PATCH 2/3] dt-bindings: pwm: rzg2l-gpt: Document > >> renesas,poegs property > >> > >> On 04/11/2022 10:59, Biju Das wrote: > >>> RZ/G2L GPT IP supports output pin disable function by dead time > >> error > >>> and detecting short-circuits between output pins. > >>> > >>> Add documentation for the optional property renesas,poegs to link a > >>> pair of GPT IOs with POEG. > >>> > >>> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > >>> --- > >>> .../bindings/pwm/renesas,rzg2l-gpt.yaml | 19 > >> +++++++++++++++++++ > >>> 1 file changed, 19 insertions(+) > >>> > >>> diff --git > >>> a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml > >>> b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml > >>> index 620d5ae4ae30..32f9deae89e5 100644 > >>> --- a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml > >>> +++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml > >>> @@ -245,6 +245,24 @@ properties: > >>> resets: > >>> maxItems: 1 > >>> > >>> + renesas,poegs: > >>> + $ref: "/schemas/types.yaml#/definitions/phandle-array" > >> > >> No need for quotes. > >> > >>> + items: > >> > >> You miss here maxItems... but if you have just one item, then below > >> "items" should be " - items" > >> > >>> + items: > >>> + - description: phandle to POEG instance that serves the > >> output disable > >>> + - description: An index identifying pair of GPT channels. > >>> + <0> - GPT channels 0 and 1 > >>> + <1> - GPT channels 2 and 3 > >>> + <2> - GPT channels 4 and 5 > >>> + <3> - GPT channels 6 and 7 > >>> + <4> - GPT channels 8 and 9 > >>> + <5> - GPT channels 10 and 11 > >>> + <6> - GPT channels 12 and 13 > >>> + <7> - GPT channels 14 and 15 > >> > >> then this could bave enum or minimum/maximum. Can you try if these > >> work? > > > > Yes, checks are passing with below changes. > > Will send V2 later once I get feedback for driver changes/ from other > reviewers. > > > > renesas,poegs: > > - $ref: "/schemas/types.yaml#/definitions/phandle-array" > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > items: > > + maxItems: 8 > > and it might also require minItems: 1 OK will send V2 with these changes. Cheers, Biju
diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml index 620d5ae4ae30..32f9deae89e5 100644 --- a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml +++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml @@ -245,6 +245,24 @@ properties: resets: maxItems: 1 + renesas,poegs: + $ref: "/schemas/types.yaml#/definitions/phandle-array" + items: + items: + - description: phandle to POEG instance that serves the output disable + - description: An index identifying pair of GPT channels. + <0> - GPT channels 0 and 1 + <1> - GPT channels 2 and 3 + <2> - GPT channels 4 and 5 + <3> - GPT channels 6 and 7 + <4> - GPT channels 8 and 9 + <5> - GPT channels 10 and 11 + <6> - GPT channels 12 and 13 + <7> - GPT channels 14 and 15 + description: + A list of phandle and channel index pair tuples to the POEGs that handle the + output disable for the GPT channels. + required: - compatible - reg @@ -375,4 +393,5 @@ examples: power-domains = <&cpg>; resets = <&cpg R9A07G044_GPT_RST_C>; #pwm-cells = <2>; + renesas,poegs = <&poeggd 4>; };
RZ/G2L GPT IP supports output pin disable function by dead time error and detecting short-circuits between output pins. Add documentation for the optional property renesas,poegs to link a pair of GPT IOs with POEG. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- .../bindings/pwm/renesas,rzg2l-gpt.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)