| Message ID | 20220927195842.44641-2-gerhard@engleder-embedded.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | tsnep: multi queue support and some other improvements | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On Tue, 27 Sep 2022 21:58:37 +0200, Gerhard Engleder wrote: > Within SoCs like ZynqMP, FPGA logic can be connected to different kinds > of AXI master ports. Also cache coherent AXI master ports are available. > The property "dma-coherent" is used to signal that DMA is cache > coherent. > > Add "dma-coherent" property to allow the configuration of cache coherent > DMA. > > Signed-off-by: Gerhard Engleder <gerhard@engleder-embedded.com> > --- > Documentation/devicetree/bindings/net/engleder,tsnep.yaml | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/net/engleder,tsnep.yaml b/Documentation/devicetree/bindings/net/engleder,tsnep.yaml index d0e1476e15b5..37e08ee744a8 100644 --- a/Documentation/devicetree/bindings/net/engleder,tsnep.yaml +++ b/Documentation/devicetree/bindings/net/engleder,tsnep.yaml @@ -22,6 +22,8 @@ properties: interrupts: maxItems: 1 + dma-coherent: true + local-mac-address: true mac-address: true
Within SoCs like ZynqMP, FPGA logic can be connected to different kinds of AXI master ports. Also cache coherent AXI master ports are available. The property "dma-coherent" is used to signal that DMA is cache coherent. Add "dma-coherent" property to allow the configuration of cache coherent DMA. Signed-off-by: Gerhard Engleder <gerhard@engleder-embedded.com> --- Documentation/devicetree/bindings/net/engleder,tsnep.yaml | 2 ++ 1 file changed, 2 insertions(+)