| Message ID | 20220922195651.345369-6-krzysztof.kozlowski@linaro.org |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | pinctrl/arm64: qcom: continued - fix Qualcomm LPASS pinctrl schema warnings | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On Thu, 22 Sep 2022 21:56:44 +0200, Krzysztof Kozlowski wrote: > The LPASS pin controller follows generic pin-controller bindings, so > just like TLMM, should have subnodes with '-state' and '-pins'. > > qcom/qrb5165-rb5.dtb: pinctrl@33c0000: wsa-swr-active-pins: 'pins' is a required property > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- > .../qcom,sm8250-lpass-lpi-pinctrl.yaml | 36 +++++++++++++++++-- > 1 file changed, 34 insertions(+), 2 deletions(-) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml index 06efb1382876..9640d1110fdd 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml @@ -42,9 +42,17 @@ properties: gpio-ranges: maxItems: 1 -#PIN CONFIGURATION NODES patternProperties: - '-pins$': + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm8250-lpass-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm8250-lpass-tlmm-state" + additionalProperties: false + +$defs: + qcom-sm8250-lpass-tlmm-state: type: object description: Pinctrl node's client devices use subnodes for desired pin configuration. @@ -130,4 +138,28 @@ examples: gpio-controller; #gpio-cells = <2>; gpio-ranges = <&lpi_tlmm 0 0 14>; + + wsa-swr-active-state { + clk-pins { + pins = "gpio10"; + function = "wsa_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio11"; + function = "wsa_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + }; + }; + + tx-swr-sleep-clk-state { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <2>; + bias-pull-down; + }; };
The LPASS pin controller follows generic pin-controller bindings, so just like TLMM, should have subnodes with '-state' and '-pins'. qcom/qrb5165-rb5.dtb: pinctrl@33c0000: wsa-swr-active-pins: 'pins' is a required property Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- .../qcom,sm8250-lpass-lpi-pinctrl.yaml | 36 +++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-)