| Message ID | 20220916133145.1910549-1-jean-philippe@linaro.org |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | dt-bindings: iommu: arm,smmu-v3: Relax order of interrupt names | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | warning | total: 0 errors, 1 warnings, 21 lines checked |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On 16/09/2022 15:31, Jean-Philippe Brucker wrote: > The QEMU devicetree uses a different order for SMMUv3 interrupt names, > and there isn't a good reason for enforcing a specific order. Since all > interrupt lines are optional, operating systems should not expect a > fixed interrupt array layout; they should instead match each interrupt > to its name individually. Besides, as a result of commit e4783856a2e8 > ("dt-bindings: iommu: arm,smmu-v3: make PRI IRQ optional"), "cmdq-sync" > and "priq" are already permutable. Relax the interrupt-names array > entirely by allowing any permutation, incidentally making the schema > more readable. > > Note that dt-validate won't allow duplicate names here so we don't need > to specify maxItems or add additional checks, it's quite neat. Nice explanation, much appriecated! Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On Fri, Sep 16, 2022 at 02:31:47PM +0100, Jean-Philippe Brucker wrote: > The QEMU devicetree uses a different order for SMMUv3 interrupt names, > and there isn't a good reason for enforcing a specific order. Since all > interrupt lines are optional, operating systems should not expect a > fixed interrupt array layout; they should instead match each interrupt > to its name individually. Besides, as a result of commit e4783856a2e8 > ("dt-bindings: iommu: arm,smmu-v3: make PRI IRQ optional"), "cmdq-sync" > and "priq" are already permutable. Relax the interrupt-names array > entirely by allowing any permutation, incidentally making the schema > more readable. > > Note that dt-validate won't allow duplicate names here so we don't need > to specify maxItems or add additional checks, it's quite neat. > > Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> > --- > .../devicetree/bindings/iommu/arm,smmu-v3.yaml | 15 +++++---------- > 1 file changed, 5 insertions(+), 10 deletions(-) > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml > index c57a53d87e4e..75fcf4cb52d9 100644 > --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml > @@ -39,16 +39,11 @@ properties: > any others. > - minItems: 1 > items: > - - enum: > - - eventq # Event Queue not empty > - - gerror # Global Error activated > - - const: gerror > - - enum: > - - cmdq-sync # CMD_SYNC complete > - - priq # PRI Queue not empty > - - enum: > - - cmdq-sync > - - priq > + enum: > + - eventq # Event Queue not empty > + - gerror # Global Error activated > + - cmdq-sync # CMD_SYNC complete > + - priq # PRI Queue not empty > > '#iommu-cells': > const: 1 Acked-by: Will Deacon <will@kernel.org> Joerg -- please can you take this one directly for 6.1? I don't actually have any other SMMU patches queued, so it doesn't seem worth sending a pull request just for this. Cheers, Will
On Thu, Sep 22, 2022 at 10:08:56PM +0100, Will Deacon wrote: > Acked-by: Will Deacon <will@kernel.org> > > Joerg -- please can you take this one directly for 6.1? I don't actually > have any other SMMU patches queued, so it doesn't seem worth sending a pull > request just for this. Applied, thanks.
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml index c57a53d87e4e..75fcf4cb52d9 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml @@ -39,16 +39,11 @@ properties: any others. - minItems: 1 items: - - enum: - - eventq # Event Queue not empty - - gerror # Global Error activated - - const: gerror - - enum: - - cmdq-sync # CMD_SYNC complete - - priq # PRI Queue not empty - - enum: - - cmdq-sync - - priq + enum: + - eventq # Event Queue not empty + - gerror # Global Error activated + - cmdq-sync # CMD_SYNC complete + - priq # PRI Queue not empty '#iommu-cells': const: 1
The QEMU devicetree uses a different order for SMMUv3 interrupt names, and there isn't a good reason for enforcing a specific order. Since all interrupt lines are optional, operating systems should not expect a fixed interrupt array layout; they should instead match each interrupt to its name individually. Besides, as a result of commit e4783856a2e8 ("dt-bindings: iommu: arm,smmu-v3: make PRI IRQ optional"), "cmdq-sync" and "priq" are already permutable. Relax the interrupt-names array entirely by allowing any permutation, incidentally making the schema more readable. Note that dt-validate won't allow duplicate names here so we don't need to specify maxItems or add additional checks, it's quite neat. Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> --- .../devicetree/bindings/iommu/arm,smmu-v3.yaml | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-)