| Message ID | 20220826192424.3216734-1-l.stach@pengutronix.de |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | [1/4] dt-bindings: display: imx: add binding for i.MX8MP HDMI TX | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | warning | total: 0 errors, 1 warnings, 74 lines checked |
| robh/patch-applied | success | |
| robh/dt-meta-schema | fail | build log |
Hi Lucas, Thank you for the patch. On Fri, Aug 26, 2022 at 09:24:21PM +0200, Lucas Stach wrote: > The HDMI TX controller on the i.MX8MP SoC is a Synopsys designware IP > core with a little bit of SoC integration around it. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > Tested-by: Marek Vasut <marex@denx.de> > --- > .../bindings/display/imx/fsl,imx8mp-hdmi.yaml | 74 +++++++++++++++++++ > 1 file changed, 74 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml > > diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml > new file mode 100644 > index 000000000000..14f7cd47209c > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml > @@ -0,0 +1,74 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/imx/fsl,imx8mp-hdmi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Freescale i.MX8MP DWC HDMI TX Encoder > + > +maintainers: > + - Lucas Stach <l.stach@pengutronix.de> > + > +description: | > + The HDMI transmitter is a Synopsys DesignWare HDMI 2.0 TX controller IP. > + > +allOf: > + - $ref: ../bridge/synopsys,dw-hdmi.yaml# > + > +properties: > + compatible: > + enum: > + - fsl,imx8mp-hdmi > + > + reg: > + maxItems: 1 > + > + reg-io-width: > + const: 1 > + > + clocks: > + maxItems: 5 > + > + clock-names: > + items: > + - {} > + - {} I assume these are not named as synopsys,dw-hdmi.yaml already checks them, but would it hurt to list them here for clarity ? I don't mind much either way. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > + - const: cec > + - const: pix > + - const: fdcc > + > + interrupts: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - interrupts > + - power-domains > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/clock/imx8mp-clock.h> > + #include <dt-bindings/power/imx8mp-power.h> > + > + hdmi@32fd8000 { > + compatible = "fsl,imx8mp-hdmi"; > + reg = <0x32fd8000 0x7eff>; > + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MP_CLK_HDMI_APB>, > + <&clk IMX8MP_CLK_HDMI_REF_266M>, > + <&clk IMX8MP_CLK_HDMI_FDCC_TST>, > + <&clk IMX8MP_CLK_32K>, > + <&hdmi_tx_phy>; > + clock-names = "iahb", "isfr", "fdcc", "cec", "pix"; > + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>; > + reg-io-width = <1>; > + };
Hi Lucas, Thank you for the patch. On Fri, Aug 26, 2022 at 09:24:22PM +0200, Lucas Stach wrote: > Add a simple wrapper driver for the DWC HDMI bridge driver that > implements the few bits that are necessary to abstract the i.MX8MP > SoC integration. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > Tested-by: Marek Vasut <marex@denx.de> > --- > drivers/gpu/drm/bridge/imx/Kconfig | 9 ++ > drivers/gpu/drm/bridge/imx/Makefile | 2 + > drivers/gpu/drm/bridge/imx/imx8mp-hdmi.c | 141 +++++++++++++++++++++++ > 3 files changed, 152 insertions(+) > create mode 100644 drivers/gpu/drm/bridge/imx/imx8mp-hdmi.c > > diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig > index 608f47f41bcd..d828d8bfd893 100644 > --- a/drivers/gpu/drm/bridge/imx/Kconfig > +++ b/drivers/gpu/drm/bridge/imx/Kconfig > @@ -44,4 +44,13 @@ config DRM_IMX8QXP_PIXEL_LINK_TO_DPI > Choose this to enable pixel link to display pixel interface(PXL2DPI) > found in Freescale i.MX8qxp processor. > > +config DRM_IMX8MP_DW_HDMI_BRIDGE > + tristate "i.MX8MP HDMI bridge support" > + depends on OF > + depends on COMMON_CLK > + select DRM_DW_HDMI > + help > + Choose this to enable support for the internal HDMI encoder found > + on the i.MX8MP SoC. > + > endif # ARCH_MXC || COMPILE_TEST > diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile > index aa90ec8d5433..03b0074ae538 100644 > --- a/drivers/gpu/drm/bridge/imx/Makefile > +++ b/drivers/gpu/drm/bridge/imx/Makefile > @@ -7,3 +7,5 @@ obj-$(CONFIG_DRM_IMX8QXP_LDB) += imx8qxp-ldb.o > obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o > obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o > obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o > + > +obj-$(CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE) += imx8mp-hdmi.o > diff --git a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi.c b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi.c > new file mode 100644 > index 000000000000..66089bc690c8 > --- /dev/null > +++ b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi.c > @@ -0,0 +1,141 @@ > +// SPDX-License-Identifier: GPL-2.0+ > + > +/* > + * Copyright (C) 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de> > + */ > + > +#include <drm/bridge/dw_hdmi.h> > +#include <drm/drm_modes.h> > +#include <linux/clk.h> > +#include <linux/mod_devicetable.h> > +#include <linux/module.h> > +#include <linux/platform_device.h> > + > +struct imx_hdmi { The driver is specific to the i.MX8MP, so I'd name the structure imx8mp_hdmi. Same for the probe and remove functions and for imx_dw_hdmi_of_table. > + struct dw_hdmi_plat_data plat_data; > + struct dw_hdmi *dw_hdmi; > + struct clk *pixclk; > + struct clk *fdcc; > +}; > + > +static enum drm_mode_status > +imx8mp_hdmi_mode_valid(struct dw_hdmi *dw_hdmi, void *data, > + const struct drm_display_info *info, > + const struct drm_display_mode *mode) > +{ > + struct imx_hdmi *hdmi = (struct imx_hdmi *)data; > + > + if (mode->clock < 13500) > + return MODE_CLOCK_LOW; > + > + if (mode->clock > 297000) > + return MODE_CLOCK_HIGH; > + > + if (clk_round_rate(hdmi->pixclk, mode->clock * 1000) != > + mode->clock * 1000) > + return MODE_CLOCK_RANGE; I wonder if we need some tolerance here. It can be done later. > + > + /* We don't support double-clocked and Interlaced modes */ > + if ((mode->flags & DRM_MODE_FLAG_DBLCLK) || > + (mode->flags & DRM_MODE_FLAG_INTERLACE)) > + return MODE_BAD; > + > + return MODE_OK; > +} > + > +static int imx8mp_hdmi_phy_init(struct dw_hdmi *dw_hdmi, void *data, > + const struct drm_display_info *display, > + const struct drm_display_mode *mode) > +{ > + return 0; > +} > + > +static void imx8mp_hdmi_phy_disable(struct dw_hdmi *dw_hdmi, void *data) > +{ > +} > + > +static const struct dw_hdmi_phy_ops imx8mp_hdmi_phy_ops = { > + .init = imx8mp_hdmi_phy_init, > + .disable = imx8mp_hdmi_phy_disable, > + .read_hpd = dw_hdmi_phy_read_hpd, > + .update_hpd = dw_hdmi_phy_update_hpd, > + .setup_hpd = dw_hdmi_phy_setup_hpd, > +}; > + > +static int imx_dw_hdmi_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct dw_hdmi_plat_data *plat_data; > + struct imx_hdmi *hdmi; > + int ret; > + > + hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); > + if (!hdmi) > + return -ENOMEM; > + > + plat_data = &hdmi->plat_data; > + > + hdmi->pixclk = devm_clk_get(dev, "pix"); > + if (IS_ERR(hdmi->pixclk)) > + return dev_err_probe(dev, PTR_ERR(hdmi->pixclk), > + "Unable to get pixel clock\n"); > + > + hdmi->fdcc = devm_clk_get(dev, "fdcc"); > + if (IS_ERR(hdmi->fdcc)) > + return dev_err_probe(dev, PTR_ERR(hdmi->fdcc), > + "Unable to get FDCC clock\n"); > + > + ret = clk_prepare_enable(hdmi->fdcc); Any chance to handle this through runtime PM (or through something else, depending on what the clock is) to avoid leaving it enabled all the time ? > + if (ret) > + return dev_err_probe(dev, ret, "Unable to enable FDCC clock\n"); > + > + plat_data->mode_valid = imx8mp_hdmi_mode_valid; > + plat_data->phy_ops = &imx8mp_hdmi_phy_ops; > + plat_data->phy_name = "SAMSUNG HDMI TX PHY"; > + plat_data->priv_data = hdmi; > + > + hdmi->dw_hdmi = dw_hdmi_probe(pdev, plat_data); > + if (IS_ERR(hdmi->dw_hdmi)) You need to disable the fdcc clock here. > + return PTR_ERR(hdmi->dw_hdmi); > + > + /* > + * Just release PHY core from reset, all other power management is done > + * by the PHY driver. > + */ > + dw_hdmi_phy_gen1_reset(hdmi->dw_hdmi); Any risk of race condition where the PHY wouldn't be released out of reset before the HDMI bridge is used, as you call dw_hdmi_probe() first ? > + > + platform_set_drvdata(pdev, hdmi); > + > + return 0; > +} > + > +static int imx_dw_hdmi_remove(struct platform_device *pdev) > +{ > + struct imx_hdmi *hdmi = platform_get_drvdata(pdev); > + > + dw_hdmi_remove(hdmi->dw_hdmi); > + > + clk_disable_unprepare(hdmi->fdcc); > + > + return 0; > +} > + > +static const struct of_device_id imx_dw_hdmi_of_table[] = { > + { .compatible = "fsl,imx8mp-hdmi" }, > + { /* Sentinel */ }, > +}; > +MODULE_DEVICE_TABLE(of, imx_dw_hdmi_of_table); > + > +static struct platform_driver im_dw_hdmi_platform_driver = { This one is even missing the x from imx :-) imxmp_dw_hdmi_platform_driver for coherency with the rest. > + .probe = imx_dw_hdmi_probe, > + .remove = imx_dw_hdmi_remove, > + .driver = { > + .name = "imx-dw-hdmi", > + .of_match_table = imx_dw_hdmi_of_table, > + }, > +}; > + > +module_platform_driver(im_dw_hdmi_platform_driver); > + > +MODULE_DESCRIPTION("i.MX8M HDMI encoder driver"); s/i.MX8M/i.MX8MP/ With these issues addressed, Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > +MODULE_LICENSE("GPL");
On 26/08/2022 22:24, Lucas Stach wrote: > The HDMI TX controller on the i.MX8MP SoC is a Synopsys designware IP > core with a little bit of SoC integration around it. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > Tested-by: Marek Vasut <marex@denx.de> What tested-by means in the terms of bindings? What tests were applied exactly? > --- > .../bindings/display/imx/fsl,imx8mp-hdmi.yaml | 74 +++++++++++++++++++ > 1 file changed, 74 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml > > diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml > new file mode 100644 > index 000000000000..14f7cd47209c > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml > @@ -0,0 +1,74 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/imx/fsl,imx8mp-hdmi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Freescale i.MX8MP DWC HDMI TX Encoder > + > +maintainers: > + - Lucas Stach <l.stach@pengutronix.de> > + > +description: | > + The HDMI transmitter is a Synopsys DesignWare HDMI 2.0 TX controller IP. > + > +allOf: > + - $ref: ../bridge/synopsys,dw-hdmi.yaml# > + > +properties: > + compatible: > + enum: > + - fsl,imx8mp-hdmi > + > + reg: > + maxItems: 1 > + > + reg-io-width: > + const: 1 > + > + clocks: > + maxItems: 5 > + > + clock-names: > + items: > + - {} > + - {} Clocks should be strictly defined. > + - const: cec > + - const: pix > + - const: fdcc > + > + interrupts: > + maxItems: 1 This is coming from synopsys. Skip it and use unevaluatedProperties:false reg actually as well... > + > + power-domains: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - interrupts > + - power-domains > + > +additionalProperties: false > + Best regards, Krzysztof
On Fri, 26 Aug 2022 21:24:21 +0200, Lucas Stach wrote: > The HDMI TX controller on the i.MX8MP SoC is a Synopsys designware IP > core with a little bit of SoC integration around it. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > Tested-by: Marek Vasut <marex@denx.de> > --- > .../bindings/display/imx/fsl,imx8mp-hdmi.yaml | 74 +++++++++++++++++++ > 1 file changed, 74 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.example.dtb: hdmi@32fd8000: clock-names:2: 'cec' was expected From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.example.dtb: hdmi@32fd8000: clock-names:3: 'pix' was expected From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.example.dtb: hdmi@32fd8000: clock-names:4: 'fdcc' was expected From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
On Fri, 26 Aug 2022 21:24:22 +0200 Lucas Stach <l.stach@pengutronix.de> wrote: > Add a simple wrapper driver for the DWC HDMI bridge driver that > implements the few bits that are necessary to abstract the i.MX8MP > SoC integration. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > Tested-by: Marek Vasut <marex@denx.de> Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Hello Lucas, On Fri, 26 Aug 2022 21:24:24 +0200 Lucas Stach <l.stach@pengutronix.de> wrote: > This IP block is found in the HDMI subsystem of the i.MX8MP SoC. It has a > full timing generator and can switch between different video sources. On > the i.MX8MP however the only supported source is the LCDIF. Reading this sentence I had assumed that the i.MX8MP does only support the LCDIF as an input to the PVI, but after having read the reference manual it does not seem to have such a limitation. Do you mean that "this driver only supports the LCDIF as an input"? > --- /dev/null > +++ b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c > @@ -0,0 +1,201 @@ > +// SPDX-License-Identifier: GPL-2.0+ > + > +/* > + * Copyright (C) 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de> > + */ > + > +#include <drm/drm_atomic_helper.h> > +#include <drm/drm_bridge.h> > +#include <drm/drm_crtc.h> > +#include <linux/module.h> > +#include <linux/of_device.h> > +#include <linux/of_graph.h> > +#include <linux/pm_runtime.h> > + > +#define HTX_PVI_CTL 0x0 > +#define PVI_CTL_OP_VSYNC_POL BIT(18) > +#define PVI_CTL_OP_HSYNC_POL BIT(17) > +#define PVI_CTL_OP_DE_POL BIT(16) > +#define PVI_CTL_INP_VSYNC_POL BIT(14) > +#define PVI_CTL_INP_HSYNC_POL BIT(13) > +#define PVI_CTL_INP_DE_POL BIT(12) > +#define PVI_CTL_INPUT_LCDIF BIT(2) According to the reference manual there is actually a 2-bit field here: HTX_PVI_MOD, using bits 2:1, and whose "LCDIF" value is 0b10. Thus while it obviously won't change the resulting code, it seems more correct to define this as (2 << 1). > +static void imx_hdmi_pvi_bridge_enable(struct drm_bridge *bridge, > + struct drm_bridge_state *bridge_state) > +{ > + struct drm_atomic_state *state = bridge_state->base.state; > + struct imx_hdmi_pvi *pvi = to_imx_hdmi_pvi(bridge); > + struct drm_connector_state *conn_state; > + const struct drm_display_mode *mode; > + struct drm_crtc_state *crtc_state; > + struct drm_connector *connector; > + u32 bus_flags, val; > + > + connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); > + conn_state = drm_atomic_get_new_connector_state(state, connector); > + crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); > + > + if (WARN_ON(pm_runtime_resume_and_get(pvi->dev))) > + return; > + > + mode = &crtc_state->adjusted_mode; > + > + val = PVI_CTL_INPUT_LCDIF; > + > + if (mode->flags & DRM_MODE_FLAG_PVSYNC) > + val |= PVI_CTL_OP_VSYNC_POL | PVI_CTL_INP_VSYNC_POL; > + > + if (mode->flags & DRM_MODE_FLAG_PHSYNC) > + val |= PVI_CTL_OP_HSYNC_POL | PVI_CTL_INP_HSYNC_POL; > + > + if (pvi->next_bridge->timings) > + bus_flags = pvi->next_bridge->timings->input_bus_flags; > + else if (bridge_state) > + bus_flags = bridge_state->input_bus_cfg.flags; > + > + if (bus_flags & DRM_BUS_FLAG_DE_HIGH) > + val |= PVI_CTL_OP_DE_POL | PVI_CTL_INP_DE_POL; > + > + writel(val, pvi->regs + HTX_PVI_CTL); > + val |= PVI_CTL_EN; > + writel(val, pvi->regs + HTX_PVI_CTL); I guess I'm missing something here: why can't one just write the register once, with the enable bit set? I tried removing the first writel() and everything seems to work just the same. > +static void imx_hdmi_pvi_bridge_disable(struct drm_bridge *bridge, > + struct drm_bridge_state *bridge_state) > +{ > + struct imx_hdmi_pvi *pvi = to_imx_hdmi_pvi(bridge); > + > + writel(0x0, pvi->regs + HTX_PVI_CTL); A very minor nit: why not simply writel(0, ...)? With these fixed: Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> And definitely: Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml new file mode 100644 index 000000000000..14f7cd47209c --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx8mp-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8MP DWC HDMI TX Encoder + +maintainers: + - Lucas Stach <l.stach@pengutronix.de> + +description: | + The HDMI transmitter is a Synopsys DesignWare HDMI 2.0 TX controller IP. + +allOf: + - $ref: ../bridge/synopsys,dw-hdmi.yaml# + +properties: + compatible: + enum: + - fsl,imx8mp-hdmi + + reg: + maxItems: 1 + + reg-io-width: + const: 1 + + clocks: + maxItems: 5 + + clock-names: + items: + - {} + - {} + - const: cec + - const: pix + - const: fdcc + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - power-domains + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/imx8mp-clock.h> + #include <dt-bindings/power/imx8mp-power.h> + + hdmi@32fd8000 { + compatible = "fsl,imx8mp-hdmi"; + reg = <0x32fd8000 0x7eff>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_REF_266M>, + <&clk IMX8MP_CLK_HDMI_FDCC_TST>, + <&clk IMX8MP_CLK_32K>, + <&hdmi_tx_phy>; + clock-names = "iahb", "isfr", "fdcc", "cec", "pix"; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>; + reg-io-width = <1>; + };