| Message ID | 20220826192023.3216389-1-l.stach@pengutronix.de |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | [1/2] dt-bindings: phy: add binding for the i.MX8MP HDMI PHY | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On 26/08/2022 22:20, Lucas Stach wrote: > Add a DT binding for the HDMI PHY found on the i.MX8MP SoC. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > --- > .../bindings/phy/fsl,imx8mp-hdmi-phy.yaml | 63 +++++++++++++++++++ > 1 file changed, 63 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml > new file mode 100644 > index 000000000000..2118f964cad4 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml > @@ -0,0 +1,63 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/fsl,imx8mp-hdmi-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Freescale i.MX8MP HDMI PHY binding > + > +maintainers: > + - Lucas Stach <l.stach@pengutronix.de> > + > +properties: > + compatible: > + enum: > + - fsl,imx8mp-hdmi-phy > + > + reg: > + maxItems: 1 > + > + "#clock-cells": > + const: 0 > + > + clocks: > + minItems: 2 No need for minItems. > + maxItems: 2 > + Rest looks ok, so with above: Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On 26/08/2022 22:20, Lucas Stach wrote: > This adds the driver for the Samsung HDMI PHY found on the > i.MX8MP SoC. Based on downstream implementation from > Sandor Yu <Sandor.yu@nxp.com>. > > Co-developed-by: Marco Felsch <m.felsch@pengutronix.de> > Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > --- > drivers/phy/freescale/Kconfig | 6 + > drivers/phy/freescale/Makefile | 1 + > drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 699 +++++++++++++++++++ > 3 files changed, 706 insertions(+) > create mode 100644 drivers/phy/freescale/phy-fsl-samsung-hdmi.c > > diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig > index 853958fb2c06..5c2b73042dfc 100644 > --- a/drivers/phy/freescale/Kconfig > +++ b/drivers/phy/freescale/Kconfig > @@ -35,6 +35,12 @@ config PHY_FSL_IMX8M_PCIE > Enable this to add support for the PCIE PHY as found on > i.MX8M family of SOCs. > > +config PHY_FSL_SAMSUNG_HDMI_PHY > + tristate "Samsung HDMI PHY support" > + depends on OF && HAS_IOMEM > + help > + Enable this to add support for the Samsung HDMI PHY in i.MX8MP. Your bindings do not mention that this IP block comes from Samsung, so please extend the description there. Also, since this came from blocks used by Samsung, probably it shares a lot with Samsung Exynos SoC, so it would be nice to Cc maintainers of DRM DRIVERS FOR EXYNOS for some feedback. Although existing Samsung HDMI phy driver is tightly coupled with Exynos DRM drivers, so not really re-usable without huge refactoring. I did not check the register layout similarities. Best regards, Krzysztof
Hi Krzysztof, Am Sonntag, dem 28.08.2022 um 18:53 +0300 schrieb Krzysztof Kozlowski: > On 26/08/2022 22:20, Lucas Stach wrote: > > This adds the driver for the Samsung HDMI PHY found on the > > i.MX8MP SoC. Based on downstream implementation from > > Sandor Yu <Sandor.yu@nxp.com>. > > > > Co-developed-by: Marco Felsch <m.felsch@pengutronix.de> > > Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > > --- > > drivers/phy/freescale/Kconfig | 6 + > > drivers/phy/freescale/Makefile | 1 + > > drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 699 +++++++++++++++++++ > > 3 files changed, 706 insertions(+) > > create mode 100644 drivers/phy/freescale/phy-fsl-samsung-hdmi.c > > > > diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig > > index 853958fb2c06..5c2b73042dfc 100644 > > --- a/drivers/phy/freescale/Kconfig > > +++ b/drivers/phy/freescale/Kconfig > > @@ -35,6 +35,12 @@ config PHY_FSL_IMX8M_PCIE > > Enable this to add support for the PCIE PHY as found on > > i.MX8M family of SOCs. > > > > +config PHY_FSL_SAMSUNG_HDMI_PHY > > + tristate "Samsung HDMI PHY support" > > + depends on OF && HAS_IOMEM > > + help > > + Enable this to add support for the Samsung HDMI PHY in i.MX8MP. > > Your bindings do not mention that this IP block comes from Samsung, so > please extend the description there. > > Also, since this came from blocks used by Samsung, probably it shares a > lot with Samsung Exynos SoC, so it would be nice to Cc maintainers of > DRM DRIVERS FOR EXYNOS for some feedback. > > Although existing Samsung HDMI phy driver is tightly coupled with Exynos > DRM drivers, so not really re-usable without huge refactoring. I did not > check the register layout similarities. > I did take a look at the Exynos DRM HDMI driver, but this doesn't seem to have much in common with what we do here. First the Exynos driver mixes HDMI controller and PHY programming into a single driver, while the PHY supported in this driver is paired to a Designware HDMI controller on the i.MX8MP. Secondly the newest generation supported by the Exynos driver is Exynos5 which is a 20nm part, while the i.MX8MP is a 14nm part and PHYs tend to be really technology specific. I'll CC the Exynos maintainers for the next submission, in case they can provide some input, but I currently doubt that there is much overlap. Regards, Lucas
diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml new file mode 100644 index 000000000000..2118f964cad4 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/fsl,imx8mp-hdmi-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8MP HDMI PHY binding + +maintainers: + - Lucas Stach <l.stach@pengutronix.de> + +properties: + compatible: + enum: + - fsl,imx8mp-hdmi-phy + + reg: + maxItems: 1 + + "#clock-cells": + const: 0 + + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: apb + - const: ref + + "#phy-cells": + const: 0 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - "#clock-cells" + - "#phy-cells" + - clocks + - clock-names + - power-domains + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx8mp-clock.h> + #include <dt-bindings/power/imx8mp-power.h> + + phy@32fdff00 { + compatible = "fsl,imx8mp-hdmi-phy"; + reg = <0x32fdff00 0x100>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_24M>; + clock-names = "apb", "ref"; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>; + #clock-cells = <0>; + #phy-cells = <0>; + };
Add a DT binding for the HDMI PHY found on the i.MX8MP SoC. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> --- .../bindings/phy/fsl,imx8mp-hdmi-phy.yaml | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml