diff mbox series

[net-next,1/2] dt-bindings: net: tja11xx: add nxp,refclk_in property

Message ID 20220819074729.1496088-2-wei.fang@nxp.com
State Superseded, archived
Headers show
Series add interface mode select and RMII | expand

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Commit Message

Wei Fang Aug. 19, 2022, 7:47 a.m. UTC 
From: Wei Fang <wei.fang@nxp.com>

TJA110x REF_CLK can be configured as interface reference clock
intput or output when the RMII mode enabled. This patch add the
property to make the REF_CLK can be configurable.

Signed-off-by: Wei Fang <wei.fang@nxp.com>
---
 .../devicetree/bindings/net/nxp,tja11xx.yaml    | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

Comments

Krzysztof Kozlowski Aug. 19, 2022, 9:14 a.m. UTC | #1 
On 19/08/2022 10:47, wei.fang@nxp.com wrote:
> From: Wei Fang <wei.fang@nxp.com>
> 
> TJA110x REF_CLK can be configured as interface reference clock
> intput or output when the RMII mode enabled. This patch add the
> property to make the REF_CLK can be configurable.
> 
> Signed-off-by: Wei Fang <wei.fang@nxp.com>
> ---
>  .../devicetree/bindings/net/nxp,tja11xx.yaml    | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml b/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml
> index d51da24f3505..c51ee52033e8 100644
> --- a/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml
> +++ b/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml
> @@ -31,6 +31,22 @@ patternProperties:
>          description:
>            The ID number for the child PHY. Should be +1 of parent PHY.
>  
> +      nxp,rmii_refclk_in:

No underscores in properties.

> +        type: boolean
> +        description: |
> +          The REF_CLK is provided for both transmitted and receivced data

typo: received

> +          in RMII mode. This clock signal is provided by the PHY and is
> +          typically derived from an external 25MHz crystal. Alternatively,
> +          a 50MHz clock signal generated by an external oscillator can be
> +          connected to pin REF_CLK. A third option is to connect a 25MHz
> +          clock to pin CLK_IN_OUT. So, the REF_CLK should be configured
> +          as input or output according to the actual circuit connection.
> +          If present, indicates that the REF_CLK will be configured as
> +          interface reference clock input when RMII mode enabled.
> +          If not present, the REF_CLK will be configured as interface
> +          reference clock output when RMII mode enabled.
> +          Only supported on TJA1100 and TJA1101.

Then disallow it on other variants.

Shouldn't this be just "clocks" property?


Best regards,
Krzysztof
Wei Fang Aug. 19, 2022, 9:37 a.m. UTC | #2 
> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: 2022年8月19日 17:14
> To: Wei Fang <wei.fang@nxp.com>; davem@davemloft.net;
> edumazet@google.com; kuba@kernel.org; pabeni@redhat.com;
> robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; andrew@lunn.ch;
> f.fainelli@gmail.com; hkallweit1@gmail.com; linux@armlinux.org.uk
> Cc: netdev@vger.kernel.org; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org
> Subject: Re: [PATCH net-next 1/2] dt-bindings: net: tja11xx: add nxp,refclk_in
> property
> 
> On 19/08/2022 10:47, wei.fang@nxp.com wrote:
> > From: Wei Fang <wei.fang@nxp.com>
> >
> > TJA110x REF_CLK can be configured as interface reference clock intput
> > or output when the RMII mode enabled. This patch add the property to
> > make the REF_CLK can be configurable.
> >
> > Signed-off-by: Wei Fang <wei.fang@nxp.com>
> > ---
> >  .../devicetree/bindings/net/nxp,tja11xx.yaml    | 17 +++++++++++++++++
> >  1 file changed, 17 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml
> > b/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml
> > index d51da24f3505..c51ee52033e8 100644
> > --- a/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml
> > +++ b/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml
> > @@ -31,6 +31,22 @@ patternProperties:
> >          description:
> >            The ID number for the child PHY. Should be +1 of parent PHY.
> >
> > +      nxp,rmii_refclk_in:
> 
> No underscores in properties.
> 
Sorry, It's first time for me to know this.

> > +        type: boolean
> > +        description: |
> > +          The REF_CLK is provided for both transmitted and receivced
> > + data
> 
> typo: received
> 
> > +          in RMII mode. This clock signal is provided by the PHY and is
> > +          typically derived from an external 25MHz crystal. Alternatively,
> > +          a 50MHz clock signal generated by an external oscillator can be
> > +          connected to pin REF_CLK. A third option is to connect a 25MHz
> > +          clock to pin CLK_IN_OUT. So, the REF_CLK should be configured
> > +          as input or output according to the actual circuit connection.
> > +          If present, indicates that the REF_CLK will be configured as
> > +          interface reference clock input when RMII mode enabled.
> > +          If not present, the REF_CLK will be configured as interface
> > +          reference clock output when RMII mode enabled.
> > +          Only supported on TJA1100 and TJA1101.
> 
> Then disallow it on other variants.
> 
> Shouldn't this be just "clocks" property?
> 
> 
This property is to configure the pin REF_CLK of PHY as a input pin through phy register,
indicates that the REF_CLK signal is provided by an external oscillator. so I don't think it's a
"clock" property.
Krzysztof Kozlowski Aug. 19, 2022, 11:37 a.m. UTC | #3 
On 19/08/2022 12:37, Wei Fang wrote:
>>
>>> +          in RMII mode. This clock signal is provided by the PHY and is
>>> +          typically derived from an external 25MHz crystal. Alternatively,
>>> +          a 50MHz clock signal generated by an external oscillator can be
>>> +          connected to pin REF_CLK. A third option is to connect a 25MHz
>>> +          clock to pin CLK_IN_OUT. So, the REF_CLK should be configured
>>> +          as input or output according to the actual circuit connection.
>>> +          If present, indicates that the REF_CLK will be configured as
>>> +          interface reference clock input when RMII mode enabled.
>>> +          If not present, the REF_CLK will be configured as interface
>>> +          reference clock output when RMII mode enabled.
>>> +          Only supported on TJA1100 and TJA1101.
>>
>> Then disallow it on other variants.
>>
>> Shouldn't this be just "clocks" property?
>>
>>
> This property is to configure the pin REF_CLK of PHY as a input pin through phy register,
> indicates that the REF_CLK signal is provided by an external oscillator. so I don't think it's a
> "clock" property.

clocks, not clock.

You just repeated pieces of description as an counter-argument, so this
does not explain anything.

If it is external oscillator shouldn't it be represented in DTS and then
obtained by driver (clk_get + clk_prepare_enable)? Otherwise how are you
sure that clock is actually enabled? And the lack of presence of the
external clock means it is derived from PHY?

Best regards,
Krzysztof
Andrew Lunn Aug. 19, 2022, 12:44 p.m. UTC | #4 
On Fri, Aug 19, 2022 at 02:37:36PM +0300, Krzysztof Kozlowski wrote:
> On 19/08/2022 12:37, Wei Fang wrote:
> >>
> >>> +          in RMII mode. This clock signal is provided by the PHY and is
> >>> +          typically derived from an external 25MHz crystal. Alternatively,
> >>> +          a 50MHz clock signal generated by an external oscillator can be
> >>> +          connected to pin REF_CLK. A third option is to connect a 25MHz
> >>> +          clock to pin CLK_IN_OUT. So, the REF_CLK should be configured
> >>> +          as input or output according to the actual circuit connection.
> >>> +          If present, indicates that the REF_CLK will be configured as
> >>> +          interface reference clock input when RMII mode enabled.
> >>> +          If not present, the REF_CLK will be configured as interface
> >>> +          reference clock output when RMII mode enabled.
> >>> +          Only supported on TJA1100 and TJA1101.
> >>
> >> Then disallow it on other variants.
> >>
> >> Shouldn't this be just "clocks" property?
> >>
> >>
> > This property is to configure the pin REF_CLK of PHY as a input pin through phy register,
> > indicates that the REF_CLK signal is provided by an external oscillator. so I don't think it's a
> > "clock" property.
> 
> clocks, not clock.
> 
> You just repeated pieces of description as an counter-argument, so this
> does not explain anything.
> 
> If it is external oscillator shouldn't it be represented in DTS and then
> obtained by driver (clk_get + clk_prepare_enable)? Otherwise how are you
> sure that clock is actually enabled? And the lack of presence of the
> external clock means it is derived from PHY?

Using the common clock framework has been discussed in the past. But
no PHY actually does this. When the SoC provides the clock, a few PHYs
do make use of the common clock framework as clock consumers to ensure
the clock is ticking.

Plus, as the description says, this pin can be either a clock producer
or a consumer. I don't think the common clock code allows this. It is
also not something you negotiate between the MAC and PHY. The hardware
designer typically decides based on the MAC and PHY actually used. So
this is a fixed hardware property.

     Andrew
Krzysztof Kozlowski Aug. 19, 2022, 12:52 p.m. UTC | #5 
On 19/08/2022 15:44, Andrew Lunn wrote:
> On Fri, Aug 19, 2022 at 02:37:36PM +0300, Krzysztof Kozlowski wrote:
>> On 19/08/2022 12:37, Wei Fang wrote:
>>>>
>>>>> +          in RMII mode. This clock signal is provided by the PHY and is
>>>>> +          typically derived from an external 25MHz crystal. Alternatively,
>>>>> +          a 50MHz clock signal generated by an external oscillator can be
>>>>> +          connected to pin REF_CLK. A third option is to connect a 25MHz
>>>>> +          clock to pin CLK_IN_OUT. So, the REF_CLK should be configured
>>>>> +          as input or output according to the actual circuit connection.
>>>>> +          If present, indicates that the REF_CLK will be configured as
>>>>> +          interface reference clock input when RMII mode enabled.
>>>>> +          If not present, the REF_CLK will be configured as interface
>>>>> +          reference clock output when RMII mode enabled.
>>>>> +          Only supported on TJA1100 and TJA1101.
>>>>
>>>> Then disallow it on other variants.
>>>>
>>>> Shouldn't this be just "clocks" property?
>>>>
>>>>
>>> This property is to configure the pin REF_CLK of PHY as a input pin through phy register,
>>> indicates that the REF_CLK signal is provided by an external oscillator. so I don't think it's a
>>> "clock" property.
>>
>> clocks, not clock.
>>
>> You just repeated pieces of description as an counter-argument, so this
>> does not explain anything.
>>
>> If it is external oscillator shouldn't it be represented in DTS and then
>> obtained by driver (clk_get + clk_prepare_enable)? Otherwise how are you
>> sure that clock is actually enabled? And the lack of presence of the
>> external clock means it is derived from PHY?
> 
> Using the common clock framework has been discussed in the past. But
> no PHY actually does this. When the SoC provides the clock, a few PHYs
> do make use of the common clock framework as clock consumers to ensure
> the clock is ticking.

IOW, all DTSes would have a fixed clock stub without any logic usable by
Common CF (like enabling)?

> Plus, as the description says, this pin can be either a clock producer
> or a consumer. I don't think the common clock code allows this. It is
> also not something you negotiate between the MAC and PHY. The hardware
> designer typically decides based on the MAC and PHY actually used. So
> this is a fixed hardware property.

Indeed.

Anyway the property name and typo need fixes.
Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml b/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml
index d51da24f3505..c51ee52033e8 100644
--- a/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml
+++ b/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml
@@ -31,6 +31,22 @@  patternProperties:
         description:
           The ID number for the child PHY. Should be +1 of parent PHY.
 
+      nxp,rmii_refclk_in:
+        type: boolean
+        description: |
+          The REF_CLK is provided for both transmitted and receivced data
+          in RMII mode. This clock signal is provided by the PHY and is
+          typically derived from an external 25MHz crystal. Alternatively,
+          a 50MHz clock signal generated by an external oscillator can be
+          connected to pin REF_CLK. A third option is to connect a 25MHz
+          clock to pin CLK_IN_OUT. So, the REF_CLK should be configured
+          as input or output according to the actual circuit connection.
+          If present, indicates that the REF_CLK will be configured as
+          interface reference clock input when RMII mode enabled.
+          If not present, the REF_CLK will be configured as interface
+          reference clock output when RMII mode enabled.
+          Only supported on TJA1100 and TJA1101.
+
     required:
       - reg
 
@@ -44,6 +60,7 @@  examples:
 
         tja1101_phy0: ethernet-phy@4 {
             reg = <0x4>;
+            nxp,rmii_refclk_in;
         };
     };
   - |