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Mon, 15 Aug 2022 01:08:22 -0400 (EDT) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev, Palmer Dabbelt , Paul Walmsley , Albert Ou , linux-riscv@lists.infradead.org Cc: Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Samuel Holland Subject: [PATCH 02/12] dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles Date: Mon, 15 Aug 2022 00:08:05 -0500 Message-Id: <20220815050815.22340-3-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220815050815.22340-1-samuel@sholland.org> References: <20220815050815.22340-1-samuel@sholland.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The C906 and C910 are RISC-V CPU cores from T-HEAD Semiconductor. Notably, the C906 core is used in the Allwinner D1 SoC. Signed-off-by: Samuel Holland Reviewed-by: Heiko Stuebner --- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 873dd12f6e89..ce2161d9115a 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -38,6 +38,8 @@ properties: - sifive,u5 - sifive,u7 - canaan,k210 + - thead,c906 + - thead,c910 - const: riscv - items: - enum: