| Message ID | 20220729062630.5592-2-irui.wang@mediatek.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Enable two hardware jpeg encoder for MT8195 | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dt-meta-schema | fail | build log |
Il 29/07/22 08:26, Irui Wang ha scritto: > From: kyrie wu <kyrie.wu@mediatek.com> > > Add mediatek,mt8195-jpgenc compatible to binding document. > > Signed-off-by: kyrie wu <kyrie.wu@mediatek.com> > Signed-off-by: irui wang <irui.wang@mediatek.com> > --- > .../media/mediatek,mt8195-jpegenc.yaml | 139 ++++++++++++++++++ > 1 file changed, 139 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml > > diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml > new file mode 100644 > index 000000000000..d9133e6a92f8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml > @@ -0,0 +1,139 @@ ..snip.. > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/memory/mt8195-memory-port.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/clock/mt8195-clk.h> > + #include <dt-bindings/power/mt8195-power.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + jpgenc_master { What about using ranges here? The binding would look way cleaner, like: jpeg-encoder@1a030000 { .... properties .... ranges = <0x30000 0 0x1a030000 0x10000>, /* P.S.: Not tested! */ <0x1030000 0 0x1b030000 0x10000>; encoder-core@30000 { compatible = "mediatek,mt8195-jpgenc-hw"; reg = <0 0x30000 0 0x10000>; .... properties .... }; encoder-core@1030000 { compatible = "mediatek,mt8195-jpgenc-hw"; reg = <0 0x1030000 0 0x10000>; .... properties .... }; }; P.S.: Added Krzysztof to the loop. Krzysztof, can you please give an opinion on that? Thanks, Angelo > + compatible = "mediatek,mt8195-jpgenc"; > + power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; > + iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, > + <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, > + <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, > + <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + jpgenc@1a030000 { > + compatible = "mediatek,mt8195-jpgenc-hw"; > + reg = <0 0x1a030000 0 0x10000>; > + iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>, > + <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>, > + <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>, > + <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>; > + interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&vencsys CLK_VENC_JPGENC>; > + clock-names = "jpgenc"; > + power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; > + }; > + > + jpgenc@1b030000 { > + compatible = "mediatek,mt8195-jpgenc-hw"; > + reg = <0 0x1b030000 0 0x10000>; > + iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, > + <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, > + <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, > + <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; > + interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>; > + clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>; > + clock-names = "jpgenc"; > + power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; > + }; > + }; > + };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml new file mode 100644 index 000000000000..d9133e6a92f8 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegenc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek JPEG Encoder Device Tree Bindings + +maintainers: + - kyrie wu <kyrie.wu@mediatek.corp-partner.google.com> + +description: + MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs + +properties: + compatible: + items: + - const: mediatek,mt8195-jpgenc + + power-domains: + maxItems: 1 + + iommus: + maxItems: 4 + description: + Points to the respective IOMMU block with master port as argument, see + Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. + Ports are according to the HW. + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + +# Required child node: +patternProperties: + "^jpgenc@[0-9a-f]+$": + type: object + description: + The jpeg encoder hardware device node which should be added as subnodes to + the main jpeg node. + + properties: + compatible: + const: mediatek,mt8195-jpgenc-hw + + reg: + maxItems: 1 + + iommus: + minItems: 1 + maxItems: 32 + description: + List of the hardware port in respective IOMMU block for current Socs. + Refer to bindings/iommu/mediatek,iommu.yaml. + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: jpgenc + + power-domains: + maxItems: 1 + + required: + - compatible + - reg + - iommus + - interrupts + - clocks + - clock-names + - power-domains + + additionalProperties: false + +required: + - compatible + - power-domains + - iommus + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/memory/mt8195-memory-port.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/mt8195-clk.h> + #include <dt-bindings/power/mt8195-power.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + jpgenc_master { + compatible = "mediatek,mt8195-jpgenc"; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; + iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, + <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, + <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, + <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; + #address-cells = <2>; + #size-cells = <2>; + + jpgenc@1a030000 { + compatible = "mediatek,mt8195-jpgenc-hw"; + reg = <0 0x1a030000 0 0x10000>; + iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>, + <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>, + <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>, + <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>; + interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vencsys CLK_VENC_JPGENC>; + clock-names = "jpgenc"; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; + }; + + jpgenc@1b030000 { + compatible = "mediatek,mt8195-jpgenc-hw"; + reg = <0 0x1b030000 0 0x10000>; + iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, + <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, + <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, + <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; + interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>; + clock-names = "jpgenc"; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; + }; + }; + };