| Message ID | 20220723204335.750095-10-jagan@edgeble.ai |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | ARM: Add Rockchip RV1126 support | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On 23/07/2022 22:43, Jagan Teki wrote: > Document dt-bindings for Rockchip RV1126 clock controller. > > Cc: linux-clk@vger.kernel.org > Cc: Michael Turquette <mturquette@baylibre.com> > Cc: Stephen Boyd <sboyd@kernel.org> > Signed-off-by: Jagan Teki <jagan@edgeble.ai> > --- > .../bindings/clock/rockchip,rv1126-cru.yaml | 70 +++++++++++++++++++ > 1 file changed, 70 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml > > diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml > new file mode 100644 > index 000000000000..cf4f11709125 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml > @@ -0,0 +1,70 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/rockchip,rv1126-cru.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ROCKCHIP RV1126 Family Clock Control Module Binding s/Binding// > + > +maintainers: > + - Jagan Teki <jagan@edgeble.ai> > + - Finley Xiao <finley.xiao@rock-chips.com> > + - Heiko Stuebner <heiko@sntech.de> > + > +description: | You can skip '|'. No formatting in text. > + The RV1126 clock controller generates the clock and also implements a > + reset controller for SoC peripherals. > + > +properties: > + compatible: > + enum: > + - rockchip,rv1126-cru > + - rockchip,rv1126-pmucru > + > + reg: > + maxItems: 1 > + > + "#clock-cells": > + const: 1 > + > + "#reset-cells": > + const: 1 > + > + clocks: > + maxItems: 1 > + > + clock-names: > + const: xin24m > + > + rockchip,grf: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + Phandle to the syscon managing the "general register files" (GRF), > + if missing pll rates are not changeable, due to the missing pll > + lock status. > + > +required: > + - compatible > + - reg > + - "#clock-cells" > + - "#reset-cells" > + > +additionalProperties: false > + > +examples: > + - | > + pmucru: clock-controller@ff480000 { > + compatible = "rockchip,rv1126-pmucru"; > + reg = <0xff480000 0x1000>; > + rockchip,grf = <&grf>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + - | > + cru: clock-controller@ff490000 { > + compatible = "rockchip,rv1126-cru"; > + reg = <0xff490000 0x1000>; > + rockchip,grf = <&grf>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; I would keep just one example - they are the same, except compatible. Less code to manage or to fix later... With all the changes: Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml new file mode 100644 index 000000000000..cf4f11709125 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rv1126-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ROCKCHIP RV1126 Family Clock Control Module Binding + +maintainers: + - Jagan Teki <jagan@edgeble.ai> + - Finley Xiao <finley.xiao@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: | + The RV1126 clock controller generates the clock and also implements a + reset controller for SoC peripherals. + +properties: + compatible: + enum: + - rockchip,rv1126-cru + - rockchip,rv1126-pmucru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xin24m + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + pmucru: clock-controller@ff480000 { + compatible = "rockchip,rv1126-pmucru"; + reg = <0xff480000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + - | + cru: clock-controller@ff490000 { + compatible = "rockchip,rv1126-cru"; + reg = <0xff490000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + };
Document dt-bindings for Rockchip RV1126 clock controller. Cc: linux-clk@vger.kernel.org Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Jagan Teki <jagan@edgeble.ai> --- .../bindings/clock/rockchip,rv1126-cru.yaml | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml