| Message ID | 20220722151155.21100-2-prabhakar.mahadev-lad.rj@bp.renesas.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Add PHY interrupt support for ETH{0,1} on RZ/G2L and RZ/V2L SMARC EVK | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success |
On Fri, 22 Jul 2022 16:11:53 +0100, Lad Prabhakar wrote: > Add macros for NMI and IRQ0-7 interrupts which map to SPI0-8 present on > RZ/G2L (and alike) SoC's so that these can be used in the first cell of > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > v3: > * New patch as suggested by Biju and Geert. > --- > .../interrupt-controller/irqc-rzg2l.h | 25 +++++++++++++++++++ > 1 file changed, 25 insertions(+) > create mode 100644 include/dt-bindings/interrupt-controller/irqc-rzg2l.h > Acked-by: Rob Herring <robh@kernel.org>
On Fri, Jul 22, 2022 at 5:12 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Add macros for NMI and IRQ0-7 interrupts which map to SPI0-8 present on > RZ/G2L (and alike) SoC's so that these can be used in the first cell of > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > v3: > * New patch as suggested by Biju and Geert. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v6.1. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/include/dt-bindings/interrupt-controller/irqc-rzg2l.h b/include/dt-bindings/interrupt-controller/irqc-rzg2l.h new file mode 100644 index 000000000000..34ce778885a1 --- /dev/null +++ b/include/dt-bindings/interrupt-controller/irqc-rzg2l.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides constants for Renesas RZ/G2L family IRQC bindings. + * + * Copyright (C) 2022 Renesas Electronics Corp. + * + */ + +#ifndef __DT_BINDINGS_IRQC_RZG2L_H +#define __DT_BINDINGS_IRQC_RZG2L_H + +/* NMI maps to SPI0 */ +#define RZG2L_NMI 0 + +/* IRQ0-7 map to SPI1-8 */ +#define RZG2L_IRQ0 1 +#define RZG2L_IRQ1 2 +#define RZG2L_IRQ2 3 +#define RZG2L_IRQ3 4 +#define RZG2L_IRQ4 5 +#define RZG2L_IRQ5 6 +#define RZG2L_IRQ6 7 +#define RZG2L_IRQ7 8 + +#endif /* __DT_BINDINGS_IRQC_RZG2L_H */
Add macros for NMI and IRQ0-7 interrupts which map to SPI0-8 present on RZ/G2L (and alike) SoC's so that these can be used in the first cell of Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- v3: * New patch as suggested by Biju and Geert. --- .../interrupt-controller/irqc-rzg2l.h | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 include/dt-bindings/interrupt-controller/irqc-rzg2l.h